sys/arch/evbmips/loongson/dev/glxreg.h

264

#define GCSC_GLCP_GLD_MSR_CAP (GCSC_GLCP_MSR_BASE + 0x00)

sys/arch/evbmips/loongson/dev/glxreg.h

265

#define GCSC_GLCP_GLD_MSR_CONFIG (GCSC_GLCP_MSR_BASE + 0x01)

sys/arch/evbmips/loongson/dev/glxreg.h

266

#define GCSC_GLCP_GLD_MSR_SMI (GCSC_GLCP_MSR_BASE + 0x02)

sys/arch/evbmips/loongson/dev/glxreg.h

267

#define GCSC_GLCP_GLD_MSR_ERROR (GCSC_GLCP_MSR_BASE + 0x03)

sys/arch/evbmips/loongson/dev/glxreg.h

268

#define GCSC_GLCP_GLD_MSR_PM (GCSC_GLCP_MSR_BASE + 0x04)

sys/arch/evbmips/loongson/dev/glxreg.h

269

#define GCSC_GLCP_GLD_MSR_DIAG (GCSC_GLCP_MSR_BASE + 0x05)

sys/arch/evbmips/loongson/dev/glxreg.h

271

#define GCSC_GLCP_CLK_DIS_DELAY (GCSC_GLCP_MSR_BASE + 0x08)

sys/arch/evbmips/loongson/dev/glxreg.h

272

#define GCSC_GLCP_PMCLKDISABLE (GCSC_GLCP_MSR_BASE + 0x09)

sys/arch/evbmips/loongson/dev/glxreg.h

273

#define GCSC_GLCP_GLB_PM (GCSC_GLCP_MSR_BASE + 0x0b)

sys/arch/evbmips/loongson/dev/glxreg.h

274

#define GCSC_GLCP_DBGOUT (GCSC_GLCP_MSR_BASE + 0x0c)

sys/arch/evbmips/loongson/dev/glxreg.h

275

#define GCSC_GLCP_DOWSER (GCSC_GLCP_MSR_BASE + 0x0e)

sys/arch/evbmips/loongson/dev/glxreg.h

276

#define GCSC_GLCP_CLKOFF (GCSC_GLCP_MSR_BASE + 0x10)

sys/arch/evbmips/loongson/dev/glxreg.h

277

#define GCSC_GLCP_CLKACTIVE (GCSC_GLCP_MSR_BASE + 0x11)

sys/arch/evbmips/loongson/dev/glxreg.h

278

#define GCSC_GLCP_CLKDISABLE (GCSC_GLCP_MSR_BASE + 0x12)

sys/arch/evbmips/loongson/dev/glxreg.h

279

#define GCSC_GLCP_CLK4ACK (GCSC_GLCP_MSR_BASE + 0x13)

sys/arch/evbmips/loongson/dev/glxreg.h

280

#define GCSC_GLCP_SYS_RST (GCSC_GLCP_MSR_BASE + 0x14)

sys/arch/evbmips/loongson/dev/glxreg.h

281

#define GCSC_GLCP_DBGCLKCTRL (GCSC_GLCP_MSR_BASE + 0x16)

sys/arch/evbmips/loongson/dev/glxreg.h

282

#define GCSC_GLCP_CHIP_REV_ID (GCSC_GLCP_MSR_BASE + 0x17)