sys/arch/i386/pci/gcscide.c

55

#define GCSCIDE_ATAC_GLD_MSR_CAP (GCSCIDE_MSR_ATAC_BASE + 0)

sys/arch/i386/pci/gcscide.c

56

#define GCSCIDE_ATAC_GLD_MSR_CONFIG (GCSCIDE_MSR_ATAC_BASE + 0x01)

sys/arch/i386/pci/gcscide.c

57

#define GCSCIDE_ATAC_GLD_MSR_SMI (GCSCIDE_MSR_ATAC_BASE + 0x02)

sys/arch/i386/pci/gcscide.c

58

#define GCSCIDE_ATAC_GLD_MSR_ERROR (GCSCIDE_MSR_ATAC_BASE + 0x03)

sys/arch/i386/pci/gcscide.c

59

#define GCSCIDE_ATAC_GLD_MSR_PM (GCSCIDE_MSR_ATAC_BASE + 0x04)

sys/arch/i386/pci/gcscide.c

60

#define GCSCIDE_ATAC_GLD_MSR_DIAG (GCSCIDE_MSR_ATAC_BASE + 0x05)

sys/arch/i386/pci/gcscide.c

61

#define GCSCIDE_ATAC_IO_BAR (GCSCIDE_MSR_ATAC_BASE + 0x08)

sys/arch/i386/pci/gcscide.c

62

#define GCSCIDE_ATAC_RESET (GCSCIDE_MSR_ATAC_BASE + 0x10)

sys/arch/i386/pci/gcscide.c

63

#define GCSCIDE_ATAC_CH0D0_PIO (GCSCIDE_MSR_ATAC_BASE + 0x20)

sys/arch/i386/pci/gcscide.c

64

#define GCSCIDE_ATAC_CH0D0_DMA (GCSCIDE_MSR_ATAC_BASE + 0x21)

sys/arch/i386/pci/gcscide.c

65

#define GCSCIDE_ATAC_CH0D1_PIO (GCSCIDE_MSR_ATAC_BASE + 0x22)

sys/arch/i386/pci/gcscide.c

66

#define GCSCIDE_ATAC_CH0D1_DMA (GCSCIDE_MSR_ATAC_BASE + 0x23)

sys/arch/i386/pci/gcscide.c

67

#define GCSCIDE_ATAC_PCI_ABRTERR (GCSCIDE_MSR_ATAC_BASE + 0x24)