Symbol: AIPSTZ1_BASE
sys/arch/arm/imx/imx51reg.h
125
#define ESDHC1_BASE (AIPSTZ1_BASE + 0x00004000)
sys/arch/arm/imx/imx51reg.h
126
#define ESDHC2_BASE (AIPSTZ1_BASE + 0x00008000)
sys/arch/arm/imx/imx51reg.h
127
#define ESDHC3_BASE (AIPSTZ1_BASE + 0x00020000)
sys/arch/arm/imx/imx51reg.h
128
#define ESDHC4_BASE (AIPSTZ1_BASE + 0x00024000)
sys/arch/arm/imx/imx51reg.h
131
#define PWM1_BASE (AIPSTZ1_BASE + 0x03fb4000)
sys/arch/arm/imx/imx51reg.h
132
#define PWM2_BASE (AIPSTZ1_BASE + 0x03fb8000)
sys/arch/arm/imx/imx51reg.h
134
#define UART1_BASE (AIPSTZ1_BASE + 0x03fbc000)
sys/arch/arm/imx/imx51reg.h
135
#define UART2_BASE (AIPSTZ1_BASE + 0x03fc0000)
sys/arch/arm/imx/imx51reg.h
136
#define UART3_BASE (AIPSTZ1_BASE + 0x0000c000)
sys/arch/arm/imx/imx51reg.h
139
#define CCMC_BASE (AIPSTZ1_BASE + 0x03fd4000)
sys/arch/arm/imx/imx51reg.h
141
#define ECSPI1_BASE (AIPSTZ1_BASE + 0x00010000)
sys/arch/arm/imx/imx51reg.h
145
#define SSI2_BASE (AIPSTZ1_BASE + 0x00014000)
sys/arch/arm/imx/imx51reg.h
149
#define SPDIF_BASE (AIPSTZ1_BASE + 0x00028000)
sys/arch/arm/imx/imx51reg.h
152
#define PATA_UDMA_BASE (AIPSTZ1_BASE + 0x00030000)
sys/arch/arm/imx/imx51reg.h
157
#define SLM_BASE (AIPSTZ1_BASE + 0x00034000)
sys/arch/arm/imx/imx51reg.h
161
#define I2C3_BASE (AIPSTZ1_BASE + 0x00038000)
sys/arch/arm/imx/imx51reg.h
164
#define HSI2C_BASE (AIPSTZ1_BASE + 0x00038000)
sys/arch/arm/imx/imx51reg.h
168
#define SPBA_BASE (AIPSTZ1_BASE + 0x0003c000)
sys/arch/arm/imx/imx51reg.h
171
#define USBOH3_BASE (AIPSTZ1_BASE + 0x03f80000)
sys/arch/arm/imx/imx51reg.h
172
#define USBOH3_PL301_BASE (AIPSTZ1_BASE + 0x03fc4000)
sys/arch/arm/imx/imx51reg.h
246
(AIPSTZ1_BASE + (((n) <= 4) ? \
sys/arch/arm/imx/imx51reg.h
263
#define KPP_BASE (AIPSTZ1_BASE + 0x03f94000)
sys/arch/arm/imx/imx51reg.h
266
#define WDOG1_BASE (AIPSTZ1_BASE + 0x03f98000)
sys/arch/arm/imx/imx51reg.h
267
#define WDOG2_BASE (AIPSTZ1_BASE + 0x03f9c000)
sys/arch/arm/imx/imx51reg.h
270
#define GPT_BASE (AIPSTZ1_BASE + 0x03fa0000)
sys/arch/arm/imx/imx51reg.h
273
#define SRTC_BASE (AIPSTZ1_BASE + 0x03fa4000)
sys/arch/arm/imx/imx51reg.h
277
#define IOMUXC_BASE (AIPSTZ1_BASE + 0x03fa8000)
sys/arch/arm/imx/imx51reg.h
332
#define EPIT1_BASE (AIPSTZ1_BASE + 0x03FAC000)
sys/arch/arm/imx/imx51reg.h
333
#define EPIT2_BASE (AIPSTZ1_BASE + 0x03FB0000)
sys/arch/arm/imx/imx51reg.h
336
#define PWM1_BASE (AIPSTZ1_BASE + 0x03fb4000)
sys/arch/arm/imx/imx51reg.h
337
#define PWM2_BASE (AIPSTZ1_BASE + 0x03fb8000)
sys/arch/arm/imx/imx51reg.h
340
#define SRC_BASE (AIPSTZ1_BASE + 0x03fd0000)
sys/arch/arm/imx/imx51reg.h
343
#define CCM_BASE (AIPSTZ1_BASE + 0x03fd4000)
sys/arch/arm/imx/imx51reg.h
346
#define GPC_BASE (AIPSTZ1_BASE + 0x03fd8000)