sys/arch/evbarm/stand/boot2440/dm9000.c

273

val = CSR_READ_1(l, FCR);

sys/arch/evbarm/stand/boot2440/dm9000.c

274

CSR_WRITE_1(l, FCR, val | FCR_FLCE);

sys/arch/mmeye/mmeye/machdep.c

609

OUTP(FCR, 0x00); /* no FIFO mode */

sys/arch/powerpc/booke/dev/pq3nandfcm.c

132

lbc_write_4(sc->sc_obio, FCR, __SHIFTIN(command, FCR_CMD0));

sys/arch/powerpc/booke/dev/pq3nandfcm.c

215

lbc_write_4(sc->sc_obio, FCR, len);

sys/arch/powerpc/booke/dev/pq3nandfcm.c

245

lbc_write_4(sc->sc_obio, FCR, len);

sys/arch/sandpoint/stand/altboot/brdsetup.c

1155

UART_WRITE(base, FCR, 0x00);

sys/arch/sandpoint/stand/altboot/brdsetup.c

1159

UART_WRITE(base, FCR, 0x07); /* FIFO on, TXRX FIFO reset */