ETH__BIT
#define RX_STS_CE ETH__BIT(0) /* CRC Error */
#define RX_STS_COL ETH__BIT(1) /* Collision sensed during reception */
#define RX_STS_LC ETH__BIT(5) /* Late Collision (Reserved) */
#define RX_STS_OR ETH__BIT(6) /* Overrun Error */
#define RX_STS_MFL ETH__BIT(7) /* Max Frame Len Error */
#define RX_STS_SF ETH__BIT(8) /* Short Frame Error (< 64 bytes) */
#define RX_STS_FT ETH__BIT(11) /* Frame Type (1 = 802.3) */
#define RX_STS_M ETH__BIT(12) /* Missed Frame */
#define RX_STS_HE ETH__BIT(13) /* Hash Expired (manual match) */
#define RX_STS_IGMP ETH__BIT(14) /* IGMP Packet */
#define RX_STS_ES ETH__BIT(15) /* Error Summary (CE|COL|LC|OR|MFL|SF) */
#define RX_CMD_L ETH__BIT(16) /* Last - End Of Packet */
#define RX_CMD_F ETH__BIT(17) /* First - Start Of Packet */
#define RX_CMD_EI ETH__BIT(23) /* Enable Interrupt */
#define RX_CMD_AM ETH__BIT(30) /* Auto Mode */
#define RX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */
#define ETH_ESMIR_ReadOpcode ETH__BIT(26)
#define ETH_ESMIR_ReadValid ETH__BIT(27)
#define ETH_ESMIR_Busy ETH__BIT(28)
#define ETH_EPCR_PM ETH__BIT(0)
#define ETH_EPCR_RBM ETH__BIT(1)
#define ETH_EPCR_PBF ETH__BIT(2)
#define ETH_EPCR_EN ETH__BIT(7)
#define ETH_EPCR_LPBK_GET(v) ETH__BIT(v, 8, 2)
#define ETH_EPCR_FC ETH__BIT(10)
#define ETH_EPCR_HS ETH__BIT(12)
#define ETH_EPCR_HM ETH__BIT(13)
#define ETH_EPCR_HDM ETH__BIT(14)
#define ETH_EPCR_ACCS ETH__BIT(31)
#define ETH_EPCXR_IGMP ETH__BIT(0)
#define ETH_EPCXR_SPAN ETH__BIT(1)
#define ETH_EPCXR_PAR ETH__BIT(2)
#define ETH_EPCXR_PRIOrx_Override ETH__BIT(8)
#define ETH_EPCXR_DLPXen ETH__BIT(9)
#define ETH_EPCXR_FCTLen ETH__BIT(10)
#define ETH_EPCXR_FLP ETH__BIT(11)
#define ETH_EPCXR_FCTL ETH__BIT(12)
#define ETH_EPCXR_MIBclrMode ETH__BIT(16)
#define ETH_EPCXR_MIBctrMode ETH__BIT(17)
#define ETH_EPCXR_Speed ETH__BIT(18)
#define ETH_EPCXR_SpeedEn ETH__BIT(19)
#define ETH_EPCXR_RMIIEn ETH__BIT(20)
#define ETH_EPCXR_DSCPEn ETH__BIT(21)
#define ETH_EPCMR_FJ ETH__BIT(15)
#define ETH_EPSR_Speed ETH__BIT(0)
#define ETH_EPSR_Duplex ETH__BIT(1)
#define ETH_EPSR_Fctl ETH__BIT(2)
#define ETH_EPSR_Link ETH__BIT(3)
#define ETH_EPSR_Pause ETH__BIT(4)
#define ETH_EPSR_TxLow ETH__BIT(5)
#define ETH_EPSR_TxHigh ETH__BIT(6)
#define ETH_EPSR_TXinProg ETH__BIT(7)
#define ETH__MASK(bit) (ETH__BIT(bit) - 1)
#define ETH_ESPR_Limit4(v) ETH__BIT(22)
#define ETH_ESDCR_BLMR ETH__BIT(6)
#define ETH_ESDCR_BLMT ETH__BIT(7)
#define ETH_ESDCR_POVR ETH__BIT(8)
#define ETH_ESDCR_RIFB ETH__BIT(9)
#define ETH_ESDCMR_ERD ETH__BIT(7)
#define ETH_ESDCMR_AR ETH__BIT(15)
#define ETH_ESDCMR_STDH ETH__BIT(16)
#define ETH_ESDCMR_STDL ETH__BIT(17)
#define ETH_ESDCMR_TXDH ETH__BIT(23)
#define ETH_ESDCMR_TXDL ETH__BIT(24)
#define ETH_ESDCMR_AT ETH__BIT(31)
#define ETH_IR_RxBuffer ETH__BIT(0)
#define ETH_IR_TxBufferHigh ETH__BIT(2)
#define ETH_IR_TxBufferLow ETH__BIT(3)
#define ETH_IR_TxEndHigh ETH__BIT(6)
#define ETH_IR_TxEndLow ETH__BIT(7)
#define ETH_IR_RxError ETH__BIT(8)
#define ETH_IR_TxErrorHigh ETH__BIT(10)
#define ETH_IR_TxErrorLow ETH__BIT(11)
#define ETH_IR_RxOVR ETH__BIT(12)
#define ETH_IR_TxUdr ETH__BIT(13)
#define ETH_IR_RxBuffer_0 ETH__BIT(16)
#define ETH_IR_RxBuffer_1 ETH__BIT(17)
#define ETH_IR_RxBuffer_2 ETH__BIT(18)
#define ETH_IR_RxBuffer_3 ETH__BIT(19)
#define ETH_IR_RxError_0 ETH__BIT(20)
#define ETH_IR_RxError_1 ETH__BIT(21)
#define ETH_IR_RxError_2 ETH__BIT(22)
#define ETH_IR_RxError_3 ETH__BIT(23)
#define ETH_IR_MIIPhySTC ETH__BIT(28)
#define ETH_IR_SMIdone ETH__BIT(29)
#define ETH_IR_EtherIntSum ETH__BIT(31)
#define ETH_IR_Summary ETH__BIT(31)
#define TX_STS_LC ETH__BIT(5) /* Late Collision */
#define TX_STS_UR ETH__BIT(6) /* Underrun error */
#define TX_STS_RL ETH__BIT(8) /* Retransmit Limit (excession coll) */
#define TX_STS_COL ETH__BIT(9) /* Collision Occurred */
#define TX_STS_ES ETH__BIT(15) /* Error Summary (LC|UR|RL) */
#define TX_CMD_L ETH__BIT(16) /* Last - End Of Packet */
#define TX_CMD_F ETH__BIT(17) /* First - Start Of Packet */
#define TX_CMD_P ETH__BIT(18) /* Pad Packet */
#define TX_CMD_GC ETH__BIT(22) /* Generate CRC */
#define TX_CMD_EI ETH__BIT(23) /* Enable Interrupt */
#define TX_CMD_AM ETH__BIT(30) /* Auto Mode */
#define TX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */