sys/arch/arm/at91/at91emac.c

155

u = EMAC_READ(ETH_RSR);

sys/arch/arm/at91/at91emac.c

156

EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));

sys/arch/arm/at91/at91emac.c

225

EMAC_READ(ETH_RSR); // get receive status register

sys/arch/arm/at91/at91emac.c

231

EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt

sys/arch/arm/at91/at91emac.c

234

EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit

sys/arch/arm/at91/at91emac.c

241

EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt

sys/arch/arm/at91/at91emac.c

341

u = EMAC_READ(ETH_RSR);

sys/arch/arm/at91/at91emac.c

342

EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));

sys/arch/arm/at91/at91emac.c

737

u = EMAC_READ(ETH_RSR);

sys/arch/arm/at91/at91emac.c

738

EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));

sys/dev/cadence/if_cemac.c

1068

u = CEMAC_READ(ETH_RSR);

sys/dev/cadence/if_cemac.c

1069

CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));

sys/dev/cadence/if_cemac.c

184

u = CEMAC_READ(ETH_RSR);

sys/dev/cadence/if_cemac.c

185

CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));

sys/dev/cadence/if_cemac.c

280

rsr = CEMAC_READ(ETH_RSR); // get receive status register

sys/dev/cadence/if_cemac.c

289

CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA);

sys/dev/cadence/if_cemac.c

295

CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA);

sys/dev/cadence/if_cemac.c

305

CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR);

sys/dev/cadence/if_cemac.c

460

u = CEMAC_READ(ETH_RSR);

sys/dev/cadence/if_cemac.c

461

CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));