sys/arch/arm/at91/at91emac.c

233

EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver

sys/arch/arm/at91/at91emac.c

235

EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver

sys/arch/arm/at91/at91emac.c

472

EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR

sys/arch/arm/at91/at91emac.c

709

EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR

sys/arch/arm/at91/at91emac.c

763

EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);

sys/arch/arm/at91/at91emac.c

863

EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);

sys/dev/cadence/if_cemac.c

1019

CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR

sys/dev/cadence/if_cemac.c

1096

CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);

sys/dev/cadence/if_cemac.c

1200

CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);

sys/dev/cadence/if_cemac.c

293

CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);

sys/dev/cadence/if_cemac.c

297

CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);

sys/dev/cadence/if_cemac.c

630

CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR