sys/arch/arm/at91/at91emac.c

144

EMAC_WRITE(ETH_CTL, 0); // disable everything

sys/arch/arm/at91/at91emac.c

232

ctl = EMAC_READ(ETH_CTL); // get current control register value

sys/arch/arm/at91/at91emac.c

233

EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver

sys/arch/arm/at91/at91emac.c

235

EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver

sys/arch/arm/at91/at91emac.c

330

EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything

sys/arch/arm/at91/at91emac.c

347

EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);

sys/arch/arm/at91/at91emac.c

472

EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR

sys/arch/arm/at91/at91emac.c

692

device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG));

sys/arch/arm/at91/at91emac.c

709

EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR

sys/arch/arm/at91/at91emac.c

726

EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything

sys/arch/arm/at91/at91emac.c

759

uint32_t ctl = EMAC_READ(ETH_CTL);

sys/arch/arm/at91/at91emac.c

763

EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);

sys/arch/arm/at91/at91emac.c

863

EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);

sys/dev/cadence/if_cemac.c

1019

CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR

sys/dev/cadence/if_cemac.c

1053

CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything

sys/dev/cadence/if_cemac.c

1090

uint32_t ctl = CEMAC_READ(ETH_CTL);

sys/dev/cadence/if_cemac.c

1096

CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);

sys/dev/cadence/if_cemac.c

1200

CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);

sys/dev/cadence/if_cemac.c

168

CEMAC_WRITE(ETH_CTL, 0); // disable everything

sys/dev/cadence/if_cemac.c

291

ctl = CEMAC_READ(ETH_CTL);

sys/dev/cadence/if_cemac.c

293

CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);

sys/dev/cadence/if_cemac.c

297

CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);

sys/dev/cadence/if_cemac.c

436

CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything

sys/dev/cadence/if_cemac.c

630

CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR

sys/dev/cadence/if_cemac.c

954

uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX;

sys/dev/cadence/if_cemac.c

955

CEMAC_WRITE(ETH_CTL, ctl);

sys/dev/cadence/if_cemac.c

957

CEMAC_READ(ETH_CTL)));

sys/dev/cadence/if_cemac.c

978

CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG));