EMAC_WRITE
EMAC_WRITE(ETH_CTL, 0); // disable everything
EMAC_WRITE(ETH_IDR, -1); // disable interrupts
EMAC_WRITE(ETH_RBQP, 0); // clear receive
EMAC_WRITE(ETH_CFG,
EMAC_WRITE(ETH_TCR, 0); // send nothing
EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt
EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver
EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit
EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver
EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt
EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
EMAC_WRITE(ETH_IDR, -1); // disable interrupts
EMAC_WRITE(ETH_RBQP, 0); // clear receive
EMAC_WRITE(ETH_CFG,
EMAC_WRITE(ETH_TCR, 0); // send nothing
EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
EMAC_WRITE(ETH_CFG,
EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);
EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24)
EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8)
EMAC_WRITE(ETH_SA2L, 0);
EMAC_WRITE(ETH_SA2H, 0);
EMAC_WRITE(ETH_SA3L, 0);
EMAC_WRITE(ETH_SA3H, 0);
EMAC_WRITE(ETH_SA4L, 0);
EMAC_WRITE(ETH_SA4H, 0);
EMAC_WRITE(ETH_RBQP, (uint32_t)addr);
EMAC_WRITE(ETH_IDR, -1);
EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD
EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR
EMAC_WRITE(ETH_CFG, reg);
EMAC_WRITE(ETH_IER, ETH_ISR_TBRE);
EMAC_WRITE(ETH_TAR, segs->ds_addr);
EMAC_WRITE(ETH_TCR, m->m_pkthdr.len);
EMAC_WRITE(ETH_IDR, -1);
EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
EMAC_WRITE(ETH_IDR, -1); // disable interrupts
EMAC_WRITE(ETH_CFG,
EMAC_WRITE(ETH_TCR, 0); // send nothing
EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24)
EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8)
EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24)
EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8)
EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24)
EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8)
EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24)
EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8)
EMAC_WRITE(ETH_HSH, hashes[0]);
EMAC_WRITE(ETH_HSL, hashes[1]);
EMAC_WRITE(ETH_CFG, cfg);
EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);
EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0 | TMR0_TFAE_2);
EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]);
EMAC_WRITE(sc, EMAC_IALR,
EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1);
EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | RMR_TFAE_2 |
EMAC_WRITE(sc, EMAC_TMR1,
EMAC_WRITE(sc, EMAC_TRTR, TRTR_256);
EMAC_WRITE(sc, EMAC_RWMR,
EMAC_WRITE(sc, EMAC_RWMR,
EMAC_WRITE(sc, EMAC_IPGVR, 8);
EMAC_WRITE(sc, EMAC_ISER,
EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE);
EMAC_WRITE(sc, EMAC_ISER, 0);
EMAC_WRITE(sc, EMAC_MR0,
EMAC_WRITE(sc, reg + (i << 2), gaht[i]);
EMAC_WRITE(sc, EMAC_RMR, rmr);
EMAC_WRITE(sc, EMAC_MR0, MR0_SRST);
EMAC_WRITE(sc, EMAC_MR0, mr0);
EMAC_WRITE(sc, EMAC_STACR, sta_reg);
EMAC_WRITE(sc, EMAC_STACR, sta_reg);
EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1);
EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE);
EMAC_WRITE(sc, EMAC_ISR, ISR_ALL);
EMAC_WRITE(sc, EMAC_ISR, status);