EMAC_READ
u = EMAC_READ(ETH_TSR);
u = EMAC_READ(ETH_RSR);
tsr = EMAC_READ(ETH_TSR);
imr = ~EMAC_READ(ETH_IMR);
isr = EMAC_READ(ETH_ISR) & imr;
EMAC_READ(ETH_RSR); // get receive status register
ctl = EMAC_READ(ETH_CTL); // get current control register value
irq = EMAC_READ(IntStsC);
u = EMAC_READ(ETH_TSR);
u = EMAC_READ(ETH_RSR);
while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE))
*val = EMAC_READ(ETH_MAN) & ETH_MAN_DATA;
while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE))
reg = EMAC_READ(ETH_CFG);
if_statadd(ifp, if_collisions, EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL));
misses = EMAC_READ(ETH_DRFC);
device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG));
u = EMAC_READ(ETH_TSR);
u = EMAC_READ(ETH_RSR);
uint32_t ctl = EMAC_READ(ETH_CTL);
uint32_t cfg = EMAC_READ(ETH_CFG);
EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE));
rmr = EMAC_READ(sc, EMAC_RMR);
while (EMAC_READ(sc, EMAC_MR0) & MR0_SRST) {
mr0 = EMAC_READ(sc, EMAC_MR0);
while ((EMAC_READ(sc, EMAC_MR0) & (MR0_TXI | MR0_RXI)) !=
sta_reg = EMAC_READ(sc, EMAC_STACR);
if (EMAC_READ(sc, EMAC_STACR) & STACR_PHYE) {
oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC;
oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC;
status = EMAC_READ(sc, EMAC_ISR);