EMAC3_TMR0
while (((_emac3_reg_read_4(EMAC3_TMR0) & TMR0_GNP0) != 0) &&
_emac3_reg_write_4(EMAC3_TMR0, TMR0_GNP0);
return (_emac3_reg_read_4(EMAC3_TMR0) & TMR0_GNP0);