sys/arch/arm/sunxi/sunxi_sata.c

49

#define SUNXI_SATA_DMACR(port) (0x170 + AHCI_P_OFFSET(port))

sys/dev/ic/ahcisatareg.h

194

#define AHCI_P_CLB(p) (0x100 + AHCI_P_OFFSET(p)) /* command list addr */

sys/dev/ic/ahcisatareg.h

195

#define AHCI_P_CLBU(p) (0x104 + AHCI_P_OFFSET(p)) /* command list addr */

sys/dev/ic/ahcisatareg.h

196

#define AHCI_P_FB(p) (0x108 + AHCI_P_OFFSET(p)) /* FIS addr */

sys/dev/ic/ahcisatareg.h

197

#define AHCI_P_FBU(p) (0x10c + AHCI_P_OFFSET(p)) /* FIS addr */

sys/dev/ic/ahcisatareg.h

198

#define AHCI_P_IS(p) (0x110 + AHCI_P_OFFSET(p)) /* Interrupt status */

sys/dev/ic/ahcisatareg.h

199

#define AHCI_P_IE(p) (0x114 + AHCI_P_OFFSET(p)) /* Interrupt enable */

sys/dev/ic/ahcisatareg.h

218

#define AHCI_P_CMD(p) (0x118 + AHCI_P_OFFSET(p)) /* Port command/status */

sys/dev/ic/ahcisatareg.h

245

#define AHCI_P_TFD(p) (0x120 + AHCI_P_OFFSET(p)) /* Port task file data */

sys/dev/ic/ahcisatareg.h

255

#define AHCI_P_SIG(p) (0x124 + AHCI_P_OFFSET(p)) /* device signature */

sys/dev/ic/ahcisatareg.h

265

#define AHCI_P_SSTS(p) (0x128 + AHCI_P_OFFSET(p)) /* Serial ATA status */

sys/dev/ic/ahcisatareg.h

267

#define AHCI_P_SCTL(p) (0x12c + AHCI_P_OFFSET(p)) /* Serial ATA control */

sys/dev/ic/ahcisatareg.h

269

#define AHCI_P_SERR(p) (0x130 + AHCI_P_OFFSET(p)) /* Serial ATA error */

sys/dev/ic/ahcisatareg.h

271

#define AHCI_P_SACT(p) (0x134 + AHCI_P_OFFSET(p)) /* Serial ATA active */

sys/dev/ic/ahcisatareg.h

274

#define AHCI_P_CI(p) (0x138 + AHCI_P_OFFSET(p)) /* Command issued */

sys/dev/ic/ahcisatareg.h

277

#define AHCI_P_FNTF(p) (0x13c + AHCI_P_OFFSET(p)) /* SNotification */

sys/dev/ic/ahcisatareg.h

280

#define AHCI_P_FBS(p) (0x140 + AHCI_P_OFFSET(p)) /* Port task file data */