EECD_SK
v = CSR_READ(l, WMREG_EECD) & ~(EECD_SK | EECD_DI);
CSR_WRITE(l, WMREG_EECD, v | EECD_SK);
CSR_WRITE(l, WMREG_EECD, v | EECD_SK);
reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK | EECD_DI | EECD_CS);
reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_SK);
CSR_WRITE(sc, DGE_EECD, reg | EECD_SK);
reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_DO | EECD_SK);
CSR_WRITE(sc, DGE_EECD, reg | EECD_SK); /* Raise clock */
CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);
reg |= EECD_SK;
reg &= ~EECD_SK;
reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
*eecd |= EECD_SK;
*eecd &= ~EECD_SK;