ECREG_CSR_RD
ECREG_CSR_WR((ECREG_CSR_RD & EC_CSR_INTPA) | EC_CSR_AMSW);
ECREG_CSR_WR(ECREG_CSR_RD & 0);
ECREG_CSR_WR((ECREG_CSR_RD & EC_CSR_INTPA) |
ECREG_CSR_WR((ECREG_CSR_RD & EC_CSR_PA) |
switch (ECREG_CSR_RD & (EC_CSR_BBSW | EC_CSR_ABSW | EC_CSR_RBBA)) {
ECREG_CSR_WR(ECREG_CSR_RD &
ECREG_CSR_WR((ECREG_CSR_RD & EC_CSR_INTPA) |
ECREG_CSR_WR(ECREG_CSR_RD &
if (ECREG_CSR_RD & EC_CSR_JAM) {
ECREG_CSR_WR(ECREG_CSR_RD &
else if ((ECREG_CSR_RD & EC_CSR_TBSW) == 0) {
ECREG_CSR_WR(ECREG_CSR_RD &
ECREG_CSR_WR(ECREG_CSR_RD &
ECREG_CSR_WR((ECREG_CSR_RD & EC_CSR_INTPA) |
ECREG_CSR_WR((ECREG_CSR_RD & EC_CSR_INTPA) |