DSU
.reg = CLKSEL_CON(DSU, 2), \
.reg = CLKSEL_CON(DSU, 3), \
PLL_CON(DSU, 16),
CLKSEL_CON(DSU, 5),
CLKSEL_CON(DSU, 5), /* mux_reg */
CLKSEL_CON(DSU, 6), /* div0_reg */
CLKSEL_CON(DSU, 6), /* div1_reg */
CLKSEL_CON(DSU, 7), /* div2_reg */
CLKSEL_CON(DSU, 7), /* div3_reg */
.reg = CLKSEL_CON(DSU, 6 + (regoff)), \
.reg = CLKSEL_CON(DSU, 0), \
CLKSEL_CON(DSU, 0), __BITS(13,12), __BITS(4,0),
CLKGATE_CON(DSU, 0), __BIT(4),
CLKSEL_CON(DSU, 3), __BITS(4,0),
CLKGATE_CON(DSU, 1), __BIT(0),
CLKSEL_CON(DSU, 3), __BITS(9,5),
CLKGATE_CON(DSU, 1), __BIT(1),
CLKSEL_CON(DSU, 1), __BITS(15,11),
CLKGATE_CON(DSU, 0), __BIT(12),
CLKSEL_CON(DSU, 1), __BITS(5,1),
CLKGATE_CON(DSU, 0), __BIT(8),
CLKSEL_CON(DSU, 1), __BITS(10,6),
CLKGATE_CON(DSU, 0), __BIT(9),
CLKSEL_CON(DSU, 2), __BITS(4,0),
CLKGATE_CON(DSU, 0), __BIT(13),
CLKSEL_CON(DSU, 2), __BITS(9,5),
CLKGATE_CON(DSU, 0), __BIT(14),
CLKSEL_CON(DSU, 2), __BITS(14,10),
CLKGATE_CON(DSU, 0), __BIT(15),
CLKSEL_CON(DSU, 4), __BITS(12,11),
CLKGATE_CON(DSU, 2), __BIT(2),
CLKSEL_CON(DSU, 4), __BITS(6,5), __BITS(4,0),
CLKGATE_CON(DSU, 1), __BIT(3),
CLKSEL_CON(DSU, 4), __BITS(8,7),
CLKGATE_CON(DSU, 1), __BIT(4),
CLKGATE_CON(DSU, 2), 6),
CLKGATE_CON(DSU, 1), 7),
CLKGATE_CON(DSU, 1), 6),
CLKGATE_CON(DSU, 1), 8),
CLKGATE_CON(DSU, 1), 9),
CLKGATE_CON(DSU, 2), 0),
CLKGATE_CON(DSU, 2), 1),
.reg = CLKSEL_CON(DSU, 1), \