DMA_WRITE
DMA_WRITE(sc, DMA_IRQ_EN_REG, irqen);
DMA_WRITE(sc, DMA_IRQ_EN_REG, irqen);
DMA_WRITE(sc, NDMA_SRC_ADDR_REG(ch->ch_index), src);
DMA_WRITE(sc, NDMA_DEST_ADDR_REG(ch->ch_index), dst);
DMA_WRITE(sc, NDMA_BC_REG(ch->ch_index), req->dreq_segs[0].ds_len);
DMA_WRITE(sc, NDMA_CTRL_REG(ch->ch_index), cfg | NDMA_CTRL_LOAD);
DMA_WRITE(sc, DDMA_SRC_ADDR_REG(ch->ch_index), src);
DMA_WRITE(sc, DDMA_DEST_ADDR_REG(ch->ch_index), dst);
DMA_WRITE(sc, DDMA_BC_REG(ch->ch_index), req->dreq_segs[0].ds_len);
DMA_WRITE(sc, DDMA_PARA_REG(ch->ch_index), DDMA_PARA_VALUE);
DMA_WRITE(sc, DDMA_CTRL_REG(ch->ch_index), cfg | DDMA_CTRL_LOAD);
DMA_WRITE(sc, NDMA_CTRL_REG(ch->ch_index), val);
DMA_WRITE(sc, DDMA_CTRL_REG(ch->ch_index), val);
DMA_WRITE(sc, DMA_IRQ_PEND_STAS_REG, pend);
DMA_WRITE(sc, DMA_IRQ_EN_REG, 0);
DMA_WRITE(sc, DMA_IRQ_PEND_STAS_REG, ~0);
DMA_WRITE(sc, NDMA_CTRL_REG(index), 0);
DMA_WRITE(sc, DDMA_CTRL_REG(index), 0);
DMA_WRITE(sc, index < 8 ?
DMA_WRITE(sc, index < 8 ?
DMA_WRITE(sc, DMA_MODE_REG(ch->ch_index),
DMA_WRITE(sc, DMA_START_ADDR_REG(ch->ch_index),
DMA_WRITE(sc, DMA_EN_REG(ch->ch_index), DMA_EN_EN);
DMA_WRITE(sc, DMA_EN_REG(ch->ch_index), 0);
DMA_WRITE(sc, DMA_IRQ_PEND_REG0_REG, pend0);
DMA_WRITE(sc, DMA_IRQ_PEND_REG1_REG, pend1);
DMA_WRITE(sc, DMA_IRQ_EN_REG0_REG, 0);
DMA_WRITE(sc, DMA_IRQ_EN_REG1_REG, 0);
DMA_WRITE(sc, DMA_IRQ_PEND_REG0_REG, ~0);
DMA_WRITE(sc, DMA_IRQ_PEND_REG1_REG, ~0);
DMA_WRITE(sc, DMA_EN_REG(index), 0);
DMA_WRITE(sc, conf->autogate_reg, conf->autogate_mask);
outb(DMA_MODE, func == F_READ ? DMA_READ : DMA_WRITE);