DMA_WR
DMA_WR(sc, HW_APB_CTRL1_SET, (1<<chan->chan_index)<<16);
DMA_WR(sc, reg, chan->chan_ds[0].ds_addr);
DMA_WR(sc, reg, val);
DMA_WR(sc, HW_APB_CTRL2_CLR, (1<<chan->chan_index));
DMA_WR(sc, HW_APB_CTRL1_CLR, (1<<chan->chan_index));
DMA_WR(sc, HW_APB_CTRL1_CLR, (1<<chan->chan_index));
DMA_WR(sc, HW_APB_CTRL0_SET,
DMA_WR(sc, HW_APBX_CHANNEL_CTRL_SET,
DMA_WR(sc, HW_APB_CTRL0_CLR, HW_APB_CTRL0_SFTRST);
DMA_WR(sc, HW_APB_CTRL0_CLR, HW_APB_CTRL0_CLKGATE);
DMA_WR(sc, HW_APB_CTRL0_SET, HW_APB_CTRL0_SFTRST);
DMA_WR(sc, HW_APB_CTRL0_CLR, HW_APB_CTRL0_SFTRST);
DMA_WR(sc, HW_APB_CTRL0_CLR, HW_APB_CTRL0_CLKGATE);
DMA_WR(sc, HW_APBH_CTRL0_SET, HW_APBH_CTRL0_AHB_BURST8_EN);
DMA_WR(sc, HW_APBH_CTRL0_SET, HW_APBH_CTRL0_APB_BURST4_EN);