DMAC_REG_CSR
DMAC_REG_CSR, 0xff);
bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
csr = bus_space_read_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR);
bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
csr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR);
bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR),