sys/arch/arm/s3c2xx0/s3c2440_dma.c

101

struct s3c2440_dmac_channel sc_channels[DMAC_N_CHANNELS];

sys/arch/arm/s3c2xx0/s3c2440_dma.c

146

for(i = 0; i<DMAC_N_CHANNELS; i++) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

82

uint8_t dp_channel_order[DMAC_N_CHANNELS+1];

sys/arch/arm/s3c2xx0/s3c2440_dma.c

83

#define PERPH_LAST DMAC_N_CHANNELS+1

sys/arch/arm/s3c2xx0/s3c2440_dma.c

84

uint8_t dp_channel_source[DMAC_N_CHANNELS];

sys/arch/arm/xscale/pxa2x0_dmac.c

1322

chan < DMAC_N_CHANNELS; chan++, mask <<= 1) {

sys/arch/arm/xscale/pxa2x0_dmac.c

188

struct dmac_xfer_state *sc_active[DMAC_N_CHANNELS];

sys/arch/arm/xscale/pxa2x0_dmac.c

195

uint8_t p_pri[DMAC_N_CHANNELS];

sys/arch/arm/xscale/pxa2x0_dmac.c

198

uint8_t sc_channel_priority[DMAC_N_CHANNELS];

sys/arch/arm/xscale/pxa2x0_dmac.c

319

for (i = 0; i < DMAC_N_CHANNELS; i++) {

sys/arch/arm/xscale/pxa2x0_dmac.c

346

for (i = 0; i < DMAC_N_CHANNELS; i++) {