sys/arch/arm/s3c2xx0/s3c2440_dma.c

196

if (dx->dx_desc[DMAC_DESC_SRC].xd_increment) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

197

dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs--;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

198

if (dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs == 0) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

201

dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg++;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

383

dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg = dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

384

dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs = dx->dx_desc[DMAC_DESC_SRC].xd_nsegs;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

473

dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg->ds_addr);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

475

DPRINTF(("Source address: 0x%x\n", (unsigned)dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg->ds_addr));

sys/arch/arm/s3c2xx0/s3c2440_dma.c

478

if (dx->dx_desc[DMAC_DESC_SRC].xd_bus_type == DMAC_BUS_TYPE_PERIPHERAL) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

483

if (dx->dx_desc[DMAC_DESC_SRC].xd_increment) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

510

if (dx->dx_desc[DMAC_DESC_SRC].xd_increment) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

512

transfer_size = dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg->ds_len;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

515

dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg->ds_len);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

416

xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_SYSTEM;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

417

xfer->dx_desc[DMAC_DESC_SRC].xd_increment = TRUE;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

418

xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = buf->i2b_dmamap->dm_nsegs;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

419

xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = buf->i2b_dmamap->dm_segs;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

473

xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

474

xfer->dx_desc[DMAC_DESC_SRC].xd_increment = FALSE;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

475

xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

476

xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &i2s->sc_dr;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

450

xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

451

xfer->dx_desc[DMAC_DESC_SRC].xd_increment = FALSE;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

452

xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

453

xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

491

xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_SYSTEM;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

492

xfer->dx_desc[DMAC_DESC_SRC].xd_increment = TRUE;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

493

xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = cmd->c_dmamap->dm_nsegs;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

494

xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = cmd->c_dmamap->dm_segs;

sys/arch/arm/xscale/pxa2x0_ac97.c

785

dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false;

sys/arch/arm/xscale/pxa2x0_ac97.c

786

dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = ad->ad_nsegs;

sys/arch/arm/xscale/pxa2x0_ac97.c

787

dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = ad->ad_segs;

sys/arch/arm/xscale/pxa2x0_ac97.c

844

dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true;

sys/arch/arm/xscale/pxa2x0_ac97.c

845

dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;

sys/arch/arm/xscale/pxa2x0_ac97.c

846

dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr;

sys/arch/arm/xscale/pxa2x0_dmac.c

1042

src_ds = &dxs->dxs_segs[DMAC_DESC_SRC];

sys/arch/arm/xscale/pxa2x0_dmac.c

1044

src_xd = &dxs->dxs_desc[DMAC_DESC_SRC];

sys/arch/arm/xscale/pxa2x0_dmac.c

1257

if (dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs == 0 ||

sys/arch/arm/xscale/pxa2x0_dmac.c

144

#define ds_src_addr_hold ds_xfer.dxs_desc[DMAC_DESC_SRC].xd_addr_hold

sys/arch/arm/xscale/pxa2x0_dmac.c

146

#define ds_src_burst ds_xfer.dxs_desc[DMAC_DESC_SRC].xd_burst_size

sys/arch/arm/xscale/pxa2x0_dmac.c

148

#define ds_src_dma_segs ds_xfer.dxs_desc[DMAC_DESC_SRC].xd_dma_segs

sys/arch/arm/xscale/pxa2x0_dmac.c

150

#define ds_src_nsegs ds_xfer.dxs_desc[DMAC_DESC_SRC].xd_nsegs

sys/arch/arm/xscale/pxa2x0_dmac.c

837

src = &dxs->dxs_desc[DMAC_DESC_SRC];

sys/arch/arm/xscale/pxa2x0_dmac.c

842

if ((err = dmac_init_desc(&dxs->dxs_segs[DMAC_DESC_SRC], src, &size,

sys/arch/arm/xscale/pxa2x0_i2s.c

343

dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false;

sys/arch/arm/xscale/pxa2x0_i2s.c

344

dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = p->nsegs;

sys/arch/arm/xscale/pxa2x0_i2s.c

345

dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = p->segs;

sys/arch/arm/xscale/pxa2x0_i2s.c

393

dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true;

sys/arch/arm/xscale/pxa2x0_i2s.c

394

dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;

sys/arch/arm/xscale/pxa2x0_i2s.c

395

dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr;

sys/arch/arm/xscale/pxa2x0_mci.c

268

sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true;

sys/arch/arm/xscale/pxa2x0_mci.c

269

sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;

sys/arch/arm/xscale/pxa2x0_mci.c

270

sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_rxdr;

sys/arch/arm/xscale/pxa2x0_mci.c

292

sc->sc_txdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false;

sys/arch/arm/xscale/pxa2x0_mci.c

640

dx_desc = &sc->sc_txdx->dx_desc[DMAC_DESC_SRC];