sys/arch/arm/s3c2xx0/s3c2440_dma.c

204

if (dx->dx_desc[DMAC_DESC_DST].xd_increment) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

205

dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs--;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

206

if (dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs == 0) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

209

dxs->dxs_segs[DMAC_DESC_DST].ds_curseg++;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

385

dxs->dxs_segs[DMAC_DESC_DST].ds_curseg = dx->dx_desc[DMAC_DESC_DST].xd_dma_segs;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

386

dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs = dx->dx_desc[DMAC_DESC_DST].xd_nsegs;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

476

DPRINTF(("Dest. address: 0x%x\n", (unsigned)dxs->dxs_segs[DMAC_DESC_DST].ds_curseg->ds_addr));

sys/arch/arm/s3c2xx0/s3c2440_dma.c

493

dxs->dxs_segs[DMAC_DESC_DST].ds_curseg->ds_addr);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

495

if (dx->dx_desc[DMAC_DESC_DST].xd_bus_type == DMAC_BUS_TYPE_PERIPHERAL) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

500

if (dx->dx_desc[DMAC_DESC_DST].xd_increment) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

511

if (!dx->dx_desc[DMAC_DESC_DST].xd_increment) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

514

transfer_size = uimin(dxs->dxs_segs[DMAC_DESC_DST].ds_curseg->ds_len,

sys/arch/arm/s3c2xx0/s3c2440_dma.c

518

if (dx->dx_desc[DMAC_DESC_DST].xd_increment) {

sys/arch/arm/s3c2xx0/s3c2440_dma.c

519

transfer_size = dxs->dxs_segs[DMAC_DESC_DST].ds_curseg->ds_len;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

411

xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

412

xfer->dx_desc[DMAC_DESC_DST].xd_increment = FALSE;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

413

xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

414

xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = &i2s->sc_dr;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

478

xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_SYSTEM;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

479

xfer->dx_desc[DMAC_DESC_DST].xd_increment = TRUE;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

480

xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = buf->i2b_dmamap->dm_nsegs;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

481

xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = buf->i2b_dmamap->dm_segs;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

455

xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_SYSTEM;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

456

xfer->dx_desc[DMAC_DESC_DST].xd_increment = TRUE;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

457

xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = cmd->c_dmamap->dm_nsegs;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

458

xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = cmd->c_dmamap->dm_segs;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

486

xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

487

xfer->dx_desc[DMAC_DESC_DST].xd_increment = FALSE;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

488

xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;

sys/arch/arm/s3c2xx0/s3c2440_sdi.c

489

xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr;

sys/arch/arm/xscale/pxa2x0_ac97.c

788

dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true;

sys/arch/arm/xscale/pxa2x0_ac97.c

789

dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;

sys/arch/arm/xscale/pxa2x0_ac97.c

790

dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr;

sys/arch/arm/xscale/pxa2x0_ac97.c

841

dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false;

sys/arch/arm/xscale/pxa2x0_ac97.c

842

dx->dx_desc[DMAC_DESC_DST].xd_nsegs = ad->ad_nsegs;

sys/arch/arm/xscale/pxa2x0_ac97.c

843

dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = ad->ad_segs;

sys/arch/arm/xscale/pxa2x0_dmac.c

1043

dst_ds = &dxs->dxs_segs[DMAC_DESC_DST];

sys/arch/arm/xscale/pxa2x0_dmac.c

1045

dst_xd = &dxs->dxs_desc[DMAC_DESC_DST];

sys/arch/arm/xscale/pxa2x0_dmac.c

1258

dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs == 0 ||

sys/arch/arm/xscale/pxa2x0_dmac.c

145

#define ds_dst_addr_hold ds_xfer.dxs_desc[DMAC_DESC_DST].xd_addr_hold

sys/arch/arm/xscale/pxa2x0_dmac.c

147

#define ds_dst_burst ds_xfer.dxs_desc[DMAC_DESC_DST].xd_burst_size

sys/arch/arm/xscale/pxa2x0_dmac.c

149

#define ds_dst_dma_segs ds_xfer.dxs_desc[DMAC_DESC_DST].xd_dma_segs

sys/arch/arm/xscale/pxa2x0_dmac.c

151

#define ds_dst_nsegs ds_xfer.dxs_desc[DMAC_DESC_DST].xd_nsegs

sys/arch/arm/xscale/pxa2x0_dmac.c

838

dst = &dxs->dxs_desc[DMAC_DESC_DST];

sys/arch/arm/xscale/pxa2x0_dmac.c

850

if ((err = dmac_init_desc(&dxs->dxs_segs[DMAC_DESC_DST], dst, &size,

sys/arch/arm/xscale/pxa2x0_i2s.c

346

dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true;

sys/arch/arm/xscale/pxa2x0_i2s.c

347

dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;

sys/arch/arm/xscale/pxa2x0_i2s.c

348

dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr;

sys/arch/arm/xscale/pxa2x0_i2s.c

396

dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false;

sys/arch/arm/xscale/pxa2x0_i2s.c

397

dx->dx_desc[DMAC_DESC_DST].xd_nsegs = p->nsegs;

sys/arch/arm/xscale/pxa2x0_i2s.c

398

dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = p->segs;

sys/arch/arm/xscale/pxa2x0_mci.c

271

sc->sc_rxdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false;

sys/arch/arm/xscale/pxa2x0_mci.c

289

sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true;

sys/arch/arm/xscale/pxa2x0_mci.c

290

sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;

sys/arch/arm/xscale/pxa2x0_mci.c

291

sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_txdr;

sys/arch/arm/xscale/pxa2x0_mci.c

635

dx_desc = &sc->sc_rxdx->dx_desc[DMAC_DESC_DST];