sys/arch/arm/xscale/pxa2x0_dmac.c

1187

dmac_reg_write(sc, DMAC_DCSR(dxs->dxs_channel),

sys/arch/arm/xscale/pxa2x0_dmac.c

1201

dcsr = dmac_reg_read(sc, DMAC_DCSR(channel));

sys/arch/arm/xscale/pxa2x0_dmac.c

1202

dmac_reg_write(sc, DMAC_DCSR(channel), dcsr);

sys/arch/arm/xscale/pxa2x0_dmac.c

1203

if (dmac_reg_read(sc, DMAC_DCSR(channel)) & DCSR_STOPSTATE)

sys/arch/arm/xscale/pxa2x0_dmac.c

1204

dmac_reg_write(sc, DMAC_DCSR(channel), dcsr & ~DCSR_RUN);

sys/arch/arm/xscale/pxa2x0_dmac.c

320

dmac_reg_write(sc, DMAC_DCSR(i), 0);

sys/arch/arm/xscale/pxa2x0_dmac.c

928

dmac_reg_write(sc, DMAC_DCSR(dxs->dxs_channel), 0);

sys/arch/arm/xscale/pxa2x0_dmac.c

931

rv = dmac_reg_read(sc, DMAC_DCSR(dxs->dxs_channel));