DMACSR_COMPLETE
if (state & DMACSR_COMPLETE)
((state & DMACSR_COMPLETE) != 0) &&
if ((state & DMACSR_COMPLETE) != 0 &&
state &= (DMACSR_COMPLETE | DMACSR_SUPDATE | DMACSR_ENABLE);
state &= (DMACSR_BUSEXC | DMACSR_COMPLETE |
if (/* (state & DMACSR_READ) || */ (state & DMACSR_COMPLETE) == 0) {
(DMACSR_BUSEXC | DMACSR_COMPLETE
if (state & (DMACSR_COMPLETE|DMACSR_BUSEXC)) {
if ((state & DMACSR_COMPLETE) == 0 ||
(DMACSR_BUSEXC | DMACSR_COMPLETE
if (state & DMACSR_COMPLETE) {
if ((state & DMACSR_COMPLETE) == 0 ||
state = dma->dd_csr & (DMACSR_BUSEXC | DMACSR_COMPLETE
while (!(state & DMACSR_COMPLETE) && (state & DMACSR_ENABLE) && flushcount < 16)
state = dma->dd_csr & (DMACSR_BUSEXC | DMACSR_COMPLETE