DMAADDR
td[i]->buffer = DMAADDR(&xfer->ux_dmabuf, offset) | 0xa0000000;
td->buffer = DMAADDR(&reqdma,0) | 0xa0000000;
td1->buffer = DMAADDR(&xfer->ux_dmabuf,0) | 0xa0000000;
v = (DMAADDR(sc->sc_dma) >> 16) & 0xffff;
v = (unsigned long)DMAADDR(sc->sc_dma);
sc->sc_linear = (paddr_t)DMAADDR(sc->sc_dma) + 0x100000 * sc->sc_tiles_x;
h = DMAADDR(sc->sc_dmai);
auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize,
sc->pcmo.start = DMAADDR(p);
sc->pcmi.start = DMAADDR(p);
sc->pcmi.dmalist[0].base = DMAADDR(p);
"in %d segs\n", KERNADDR(dma), (uint32_t) DMAADDR(dma), dma->size,
caddr_p = DMAADDR(c_dma);
saddr_p = DMAADDR(s_dma);
next_caddr_p = DMAADDR(c_dma);
value = DMAADDR(dma);
dmaaddr = DMAADDR(chst->dma);
(void *)DMAADDR(p), (void *)p->cd_size));
DMAADDR(p));
DMAADDR(p));
*(rm++) = (DMAADDR(p) + 0 * bpl);
*(rm++) = (DMAADDR(p) + 1 * bpl);
if (DMAADDR(p) % sc->dma_align != 0 ) {
"4kB align\n", (ulong)DMAADDR(p));
BA1WRITE4(sc, CS4280_PBA, DMAADDR(p));
if (DMAADDR(p) % sc->dma_align != 0) {
"4kB align\n", (ulong)DMAADDR(p));
BA1WRITE4(sc, CS4280_CBA, DMAADDR(p));
(int)DMAADDR(p), dma_count));
BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p));
(int)DMAADDR(p), dma_count));
BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p));
*(rm++) = (DMAADDR(p) + 0 * bpl);
*(rm++) = (DMAADDR(p) + 1 * bpl);
(int)DMAADDR(p),
EWRITE4(sc, EAP_DAC2_ADDR, DMAADDR(p));
(int)DMAADDR(p),
EWRITE4(sc, EAP_DAC1_ADDR, DMAADDR(p));
(int)DMAADDR(p),
EWRITE4(sc, EAP_ADC_ADDR, DMAADDR(p));
dpmem = DMAADDR(sc->pmem);
emuxki_write(sc, 0, EMU_ADCBA, DMAADDR(sc->rmem));
emuxki_write(sc, 0, EMU_PTB, DMAADDR(sc->ptb));
bufaddr = DMAADDR(p);
bufaddr = DMAADDR(p);
(int)DMAADDR(&ess->sc_dma) + off));
DMAADDR(&ess->sc_dma) >> WAVCACHE_BASEADDR_SHIFT);
DMAADDR(&ess->sc_dma) >> WAVCACHE_BASEADDR_SHIFT);
ess->pch.base = DMAADDR(p) + MAESTRO_PLAYBUF_OFF;
ess->rch.base = DMAADDR(p) + MAESTRO_RECBUF_L_OFF;
ess->rch.base = DMAADDR(p) + MAESTRO_RECBUF_OFF;
chctl = (DMAADDR(p) + choffset - 0x10) &
device_xname(sc->sc_dev), (unsigned long)DMAADDR(ed)));
DMAADDR(ed));
device_xname(sc->sc_dev), (unsigned long)DMAADDR(ed)));
DMAADDR(ed));
rxd->addr = DMAADDR(dmap);
dma->dma_paddr = DMAADDR(dma->dma_map);
(long)p->segs[0].ds_addr, (long)KERNADDR(p), (long)DMAADDR(p)));
(int)DMAADDR(p), dma_count));
DMAADDR(p));
(int)DMAADDR(p), dma_count));
DMAADDR(p));
s = DMAADDR(p);
s = DMAADDR(p);
pa = DMAADDR(&sc->sc_ctrldata) + sc->pbankoff;
da = DMAADDR(p);
EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
const bus_addr_t baddr = DMAADDR(&dma, offs);
const bus_addr_t baddr = DMAADDR(&dma, offs);
paddr_t a = EHCI_PAGE(DMAADDR(dma,
(uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0);
const bus_addr_t baddr = DMAADDR(&dma, offs);
const bus_addr_t baddr = DMAADDR(&dma, offs);
const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0);
const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0);
const bus_addr_t sba = DMAADDR(dma_buf, offs);
const bus_addr_t eba = DMAADDR(dma_buf, offs - 1);
int addr = DMAADDR(dma_buf, froffs);
EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs))));
uint64_t page = DMAADDR(dma_buf, page_offs);
const bus_addr_t flba = DMAADDR(&sc->sc_fldma, 0);
OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
setup->td->td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0));
buf = DMAADDR(&xfer->ux_dmabuf, 0);
buf = DMAADDR(&xfer->ux_dmabuf, boff);
ohci_physaddr_t nend = DMAADDR(&xfer->ux_dmabuf, boff - 1);
sed->physaddr = DMAADDR(&dma, offs);
std->physaddr = DMAADDR(&dma, offs);
const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs);
const ohci_physaddr_t edataphys = DMAADDR(dma, edataoffs);
sitd->physaddr = DMAADDR(&dma, offs);
std->physaddr = DMAADDR(&dma, offs);
sqh->physaddr = DMAADDR(&dma, offs);
const bus_addr_t sbp = DMAADDR(dma, offs);
const bus_addr_t ebp = DMAADDR(dma, offs + l - 1);
l = PAGE_SIZE - (DMAADDR(dma, offs) & PAGE_MASK);
std->td.td_buffer = htole32(DMAADDR(dma, offs));
setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0));
buf = DMAADDR(&xfer->ux_dmabuf, offs);
DMAADDR(&xfer->ux_dmabuf, offs - 1);
UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
spbufarray[i] = htole64(DMAADDR(dma, 0));
(uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0),
(uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0),
htole64(DMAADDR(&sc->sc_spbufarray_dma, 0));
xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0));
xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0));
xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot);
parameter = DMAADDR(dma, 0);
parameter = DMAADDR(dma, offs);
parameter = DMAADDR(dma, 0);
parameter = DMAADDR(dma, 0);
return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici);
return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx);