sys/arch/evbmips/ingenic/clock.c

100

writereg(JZ_TC_TCNT(5), 0);

sys/arch/evbmips/ingenic/clock.c

101

writereg(JZ_TC_TDFR(5), 30000); /* 10ms at 48MHz / 16 */

sys/arch/evbmips/ingenic/clock.c

102

writereg(JZ_TC_TDHR(5), 60000); /* not reached */

sys/arch/evbmips/ingenic/clock.c

103

writereg(JZ_TC_TCSR(5), TCSR_EXT_EN| TCSR_DIV_16);

sys/arch/evbmips/ingenic/clock.c

104

writereg(JZ_TC_TMCR, TFR_FFLAG5);

sys/arch/evbmips/ingenic/clock.c

105

writereg(JZ_TC_TFCR, TFR_FFLAG5);

sys/arch/evbmips/ingenic/clock.c

106

writereg(JZ_TC_TESR, TESR_TCST5); /* enable timer 5 */

sys/arch/evbmips/ingenic/clock.c

113

writereg(JZ_ICMCR0, 0x0c000000); /* TCU2, OST */

sys/arch/evbmips/ingenic/clock.c

203

writereg(JZ_TC_TFCR, TFR_OSTFLAG);

sys/arch/evbmips/ingenic/clock.c

207

writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);

sys/arch/evbmips/ingenic/clock.c

219

writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);

sys/arch/evbmips/ingenic/clock.c

222

writereg(JZ_TC_TFCR, TFR_OSTFLAG);

sys/arch/evbmips/ingenic/clock.c

224

writereg(JZ_TC_TFCR, TFR_FFLAG5);

sys/arch/evbmips/ingenic/clock.c

78

writereg(JZ_TC_TFCR, TFR_OSTFLAG);

sys/arch/evbmips/ingenic/clock.c

79

writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);

sys/arch/evbmips/ingenic/clock.c

97

writereg(JZ_TC_TMCR, TFR_OSTFLAG);

sys/arch/evbmips/ingenic/clock.c

99

writereg(JZ_TC_TECR, TESR_TCST5); /* disable timer 5 */

sys/arch/evbmips/ingenic/intr.c

127

writereg(JZ_ICMR0, 0xffffffff);

sys/arch/evbmips/ingenic/intr.c

128

writereg(JZ_ICMR1, 0xffffffff);

sys/arch/evbmips/ingenic/intr.c

234

writereg(JZ_ICMSR0, 0x0c000000);

sys/arch/evbmips/ingenic/intr.c

236

writereg(JZ_ICMCR0, 0x0c000000);

sys/arch/evbmips/ingenic/intr.c

264

writereg(JZ_ICMSR0, ll);

sys/arch/evbmips/ingenic/intr.c

265

writereg(JZ_ICMSR1, hh);

sys/arch/evbmips/ingenic/intr.c

279

writereg(JZ_ICMSR0, mask);

sys/arch/evbmips/ingenic/intr.c

307

writereg(JZ_ICMSR1, mask);

sys/arch/evbmips/ingenic/intr.c

312

writereg(JZ_ICMCR0, ll);

sys/arch/evbmips/ingenic/intr.c

313

writereg(JZ_ICMCR1, hh);

sys/arch/evbmips/ingenic/intr.c

333

writereg(JZ_ICMCR1, 1 << (irq - 32));

sys/arch/evbmips/ingenic/intr.c

335

writereg(JZ_ICMCR0, 1 << irq);

sys/arch/evbmips/ingenic/intr.c

357

writereg(JZ_ICMSR1, 1 << (irq - 32));

sys/arch/evbmips/ingenic/intr.c

359

writereg(JZ_ICMSR0, 1 << irq);

sys/arch/evbmips/ingenic/machdep.c

113

writereg(JZ_TC_TECR, TESR_OST);

sys/arch/evbmips/ingenic/machdep.c

115

writereg(JZ_OST_CTRL, 0);

sys/arch/evbmips/ingenic/machdep.c

116

writereg(JZ_OST_CNT_LO, 0);

sys/arch/evbmips/ingenic/machdep.c

117

writereg(JZ_OST_CNT_HI, 0);

sys/arch/evbmips/ingenic/machdep.c

118

writereg(JZ_OST_DATA, 0xffffffff);

sys/arch/evbmips/ingenic/machdep.c

120

writereg(JZ_OST_CTRL, OSTC_EXT_EN | OSTC_MODE | OSTC_DIV_4);

sys/arch/evbmips/ingenic/machdep.c

122

writereg(JZ_TC_TESR, TESR_OST);

sys/arch/evbmips/ingenic/machdep.c

347

writereg(JZ_WDOG_TCER, 0); /* disable watchdog */

sys/arch/evbmips/ingenic/machdep.c

348

writereg(JZ_WDOG_TCNT, 0); /* reset counter */

sys/arch/evbmips/ingenic/machdep.c

349

writereg(JZ_WDOG_TDR, 128); /* wait for ~1s */

sys/arch/evbmips/ingenic/machdep.c

350

writereg(JZ_WDOG_TCSR, TCSR_RTC_EN | TCSR_DIV_256);

sys/arch/evbmips/ingenic/machdep.c

351

writereg(JZ_WDOG_TCER, TCER_ENABLE); /* fire! */

sys/arch/mips/ingenic/apbus.c

163

writereg(JZ_CLKGR1, reg);

sys/arch/mips/ingenic/apbus.c

166

writereg(JZ_ERNG, 1);

sys/arch/mips/ingenic/apbus.c

171

writereg(JZ_OPCR, reg);

sys/arch/mips/ingenic/apbus.c

259

writereg(JZ_CLKGR0, reg);

sys/arch/mips/ingenic/apbus.c

265

writereg(JZ_CLKGR1, reg);

sys/arch/mips/ingenic/ingenic_dme.c

171

writereg(JZ_GPIO_E_BASE + JZ_GPIO_FLAGC, GPIO_DME_INT_MASK);

sys/arch/mips/ingenic/ingenic_dwctwo.c

153

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_dwctwo.c

169

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_dwctwo.c

175

writereg(JZ_USBVBFIL, 0);

sys/arch/mips/ingenic/ingenic_dwctwo.c

180

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_dwctwo.c

183

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_dwctwo.c

190

writereg(JZ_OPCR, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

102

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

107

writereg(JZ_OPCR, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

112

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

117

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

122

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

127

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

131

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

136

writereg(JZ_SRBC, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

142

writereg(JZ_SRBC, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

91

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

96

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_regs.h

404

writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */

sys/arch/mips/ingenic/ingenic_regs.h

405

writereg(reg + JZ_GPIO_MASKS, mask);

sys/arch/mips/ingenic/ingenic_regs.h

406

writereg(reg + JZ_GPIO_PAT1C, mask); /* make output */

sys/arch/mips/ingenic/ingenic_regs.h

416

writereg(reg, mask);

sys/arch/mips/ingenic/ingenic_regs.h

425

writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */

sys/arch/mips/ingenic/ingenic_regs.h

426

writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */

sys/arch/mips/ingenic/ingenic_regs.h

427

writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */

sys/arch/mips/ingenic/ingenic_regs.h

428

writereg(reg + JZ_GPIO_PAT0C, mask);

sys/arch/mips/ingenic/ingenic_regs.h

437

writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */

sys/arch/mips/ingenic/ingenic_regs.h

438

writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */

sys/arch/mips/ingenic/ingenic_regs.h

439

writereg(reg + JZ_GPIO_PAT1C, mask); /* select 1 */

sys/arch/mips/ingenic/ingenic_regs.h

440

writereg(reg + JZ_GPIO_PAT0S, mask);

sys/arch/mips/ingenic/ingenic_regs.h

449

writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */

sys/arch/mips/ingenic/ingenic_regs.h

450

writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */

sys/arch/mips/ingenic/ingenic_regs.h

451

writereg(reg + JZ_GPIO_PAT1S, mask); /* select 2 */

sys/arch/mips/ingenic/ingenic_regs.h

452

writereg(reg + JZ_GPIO_PAT0C, mask);

sys/arch/mips/ingenic/ingenic_regs.h

461

writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */

sys/arch/mips/ingenic/ingenic_regs.h

462

writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */

sys/arch/mips/ingenic/ingenic_regs.h

463

writereg(reg + JZ_GPIO_PAT1S, mask); /* select 3 */

sys/arch/mips/ingenic/ingenic_regs.h

464

writereg(reg + JZ_GPIO_PAT0S, mask);

sys/arch/mips/ingenic/ingenic_regs.h

473

writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */

sys/arch/mips/ingenic/ingenic_regs.h

474

writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */

sys/arch/mips/ingenic/ingenic_regs.h

475

writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */

sys/arch/mips/ingenic/ingenic_regs.h

476

writereg(reg + JZ_GPIO_PAT0S, mask); /* trigger on high */

sys/arch/mips/ingenic/ingenic_regs.h

477

writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */

sys/arch/mips/ingenic/ingenic_regs.h

478

writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */

sys/arch/mips/ingenic/ingenic_regs.h

487

writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */

sys/arch/mips/ingenic/ingenic_regs.h

488

writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */

sys/arch/mips/ingenic/ingenic_regs.h

489

writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */

sys/arch/mips/ingenic/ingenic_regs.h

490

writereg(reg + JZ_GPIO_PAT0C, mask); /* trigger on low */

sys/arch/mips/ingenic/ingenic_regs.h

491

writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */

sys/arch/mips/ingenic/ingenic_regs.h

492

writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */

sys/arch/mips/ingenic/ingenic_regs.h

501

writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */

sys/arch/mips/ingenic/ingenic_regs.h

502

writereg(reg + JZ_GPIO_INTC, mask); /* not an interrupt */

sys/arch/mips/ingenic/ingenic_regs.h

503

writereg(reg + JZ_GPIO_PAT1S, mask); /* use as input */

sys/arch/mips/ingenic/ingenic_regs.h

504

writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it just in case */

sys/arch/sgimips/dev/dpclock.c

154

writereg(sc, DP8573A_TIMESAVE_CTL, j);

sys/arch/sgimips/dev/dpclock.c

155

writereg(sc, DP8573A_TIMESAVE_CTL, i);

sys/arch/sgimips/dev/dpclock.c

204

writereg(sc, DP8573A_TIMESAVE_CTL, j);

sys/arch/sgimips/dev/dpclock.c

205

writereg(sc, DP8573A_TIMESAVE_CTL, i);

sys/arch/sgimips/dev/dpclock.c

223

writereg(sc, DP8573A_RT_MODE, j);

sys/arch/sgimips/dev/dpclock.c

226

writereg(sc, DP8573A_COUNTERS +i, regs[DP8573A_COUNTERS + i]);

sys/arch/sgimips/dev/dpclock.c

228

writereg(sc, DP8573A_RT_MODE, i);