DGE_EECD
reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK | EECD_DI | EECD_CS);
CSR_WRITE(sc, DGE_EECD, reg);
CSR_WRITE(sc, DGE_EECD, reg | EECD_CS);
CSR_WRITE(sc, DGE_EECD, reg);
reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_SK);
CSR_WRITE(sc, DGE_EECD, reg);
CSR_WRITE(sc, DGE_EECD, reg | EECD_SK);
CSR_WRITE(sc, DGE_EECD, reg);
reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_DO | EECD_SK);
CSR_WRITE(sc, DGE_EECD, reg | EECD_SK); /* Raise clock */
rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */
CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */