sys/dev/nvmm/x86/nvmm_x86_vmx.c

3105

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, true);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3106

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3107

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3108

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3109

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3110

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3111

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3112

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3113

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3114

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3115

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3116

vmx_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false);