vme2_lcsr_read
reg = vme2_lcsr_read(sc, VME2LCSR_MASTER_ENABLE);
attr = vme2_lcsr_read(sc, VME2LCSR_MASTER_ATTR);
reg = vme2_lcsr_read(sc, VME2LCSR_MASTER_ADDRESS(range));
if (range == 3 && (reg = vme2_lcsr_read(sc, VME2LCSR_MAST4_TRANS))!=0) {
reg = vme2_lcsr_read(sc, VME2LCSR_MAST4_TRANS);
reg = vme2_lcsr_read(sc, VME2LCSR_MAST4_TRANS);
reg = vme2_lcsr_read(sc, VME2LCSR_SLAVE_CTRL);
reg = vme2_lcsr_read(sc, VME2LCSR_SLAVE_ADDRESS(range));
reg = vme2_lcsr_read(sc, VME2LCSR_SLAVE_CTRL);
reg = vme2_lcsr_read(sc, VME2LCSR_SLAVE_TRANS(range));
reg = vme2_lcsr_read(sc, VME2LCSR_SLAVE_TRANS(range));
reg = vme2_lcsr_read(sc, VME2LCSR_BOARD_CONTROL);
reg = vme2_lcsr_read(sc, VME2LCSR_IO_CONTROL);
reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) & ~VME2_MISC_STATUS_MIEN;
reg = vme2_lcsr_read(sc, VME2LCSR_TIMER_CONTROL);
reg = vme2_lcsr_read(sc, VME2LCSR_VECTOR_BASE);
reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) | VME2_MISC_STATUS_MIEN;
reg = vme2_lcsr_read(sc, iloffset);
reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE);
reg = vme2_lcsr_read(sc, iloffset);
reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE);
reg = vme2_lcsr_read(sc, iloffset);