vgar
*rp++ = vgar(ba, VDAC_DATA) << 2;
*gp++ = vgar(ba, VDAC_DATA) << 2;
*bp++ = vgar(ba, VDAC_DATA) << 2;
hvsync_pulse = vgar(ba, GREG_MISC_OUTPUT_R);
vgar(ba, VDAC_ADDRESS);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_ADDRESS);
vgaw(ba, PASS_ADDRESS_W, vgar(ba, PASS_ADDRESS) | 0x10);
vgaw(ba, PASS_ADDRESS_W, vgar(ba, PASS_ADDRESS) & 0xdf);
vgaw(ba, PASS_ADDRESS_W, vgar(ba, PASS_ADDRESS) | 0x20);
switch(vgar(gp->g_regkva, CRT_ADDRESS_R)>>2) {
vgaw(ba, SEQ_ADDRESS_W, vgar(ba, SEQ_ADDRESS_W) | 0x20);
vgar(ba, ACT_ADDRESS_RESET); \
*rp++ = vgar (ba, VDAC_DATA) << 2;
*gp++ = vgar (ba, VDAC_DATA) << 2;
*bp++ = vgar (ba, VDAC_DATA) << 2;
hvsync_pulse = vgar(ba, GREG_MISC_OUTPUT_R);
while (vgar(ba, GREG_INPUT_STATUS1_R) == 0x00) ; \
while ((vgar(ba, GREG_INPUT_STATUS1_R) & 0x08) == 0x08) ; \
while ((vgar(ba, GREG_INPUT_STATUS1_R) & 0x08) == 0x00) ; \
test = vgar(ba, GREG_INPUT_STATUS0_R);
cridx = vgar (ba, CRT_ADDRESS);
test = vgar(ba, 0x3cc);
hvsync_pulse = vgar(ba, GREG_MISC_OUTPUT_R);
while (vgar(ba, GREG_INPUT_STATUS1_R) == 0x00) ; \
while ((vgar(ba, GREG_INPUT_STATUS1_R) & 0x08) == 0x08) ; \
while ((vgar(ba, GREG_INPUT_STATUS1_R) & 0x08) == 0x00) ; \
test = vgar(ba, 0x3cc);
tmp = vgar(ba, ACT_ADDRESS_RESET);\
return vgar(ba, ACT_ADDRESS_R);
return vgar(ba, SEQ_ADDRESS_R);
return vgar(ba, CRT_ADDRESS_R);
return vgar(ba, GCT_ADDRESS_R);
tmp = vgar(ba, ACT_ADDRESS_RESET);\
return vgar(ba, ACT_ADDRESS_R);
return vgar(ba, SEQ_ADDRESS_R);
return vgar(ba, CRT_ADDRESS_R);
return vgar(ba, GCT_ADDRESS_R);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
(vgar(ba, CRT_ADDRESS_R) & 0x7f)
return vgar(ba, HDR) + vgar(ba, HDR) + vgar(ba, HDR) + vgar(ba, HDR);
check.cc[0] = vgar(ba, VDAC_XDATA);
check.cc[1] = vgar(ba, VDAC_XDATA);
check.cc[2] = vgar(ba, VDAC_XDATA);
check.cc[3] = vgar(ba, VDAC_XDATA);
if (vgar(ba, VDAC_XDATA) == 0x01) {
if (vgar(ba, HDR) == 0xff) {
0xc0 | vgar(ba, CRT_ADDRESS_R + 0x0fff));
if (((vgar(ba, GREG_FEATURE_CONTROL_R) & 12) |
(vgar(ba, GREG_STATUS0_R) & 0x60)) == 0x24) {
*rp++ = vgar(ba, MERLIN_VDAC_COLORS);
*gp++ = vgar(ba, MERLIN_VDAC_COLORS);
*bp++ = vgar(ba, MERLIN_VDAC_COLORS);
*rp++ = vgar(ba, VDAC_DATA+((ettype==DOMINO)?0x0fff:0)) << etcmap_shift;
*gp++ = vgar(ba, VDAC_DATA+((ettype==DOMINO)?0x0fff:0)) << etcmap_shift;
*bp++ = vgar(ba, VDAC_DATA+((ettype==DOMINO)?0x0fff:0)) << etcmap_shift;
if(vgar(ba, GREG_STATUS1_R)); \
(vgar(ba, MERLIN_VDAC_DATA) & 0x0f)); \
if(vgar(ba, GREG_STATUS1_R));
return vgar (ba, ACT_ADDRESS_R);
return vgar (ba, SEQ_ADDRESS_R);
return vgar (ba, CRT_ADDRESS_R);
return vgar (ba, GCT_ADDRESS_R);
vgar(ba, ACT_ADDRESS_RESET);
vgar(ba, ACT_ADDRESS_RESET);
vgar(ba, ACT_ADDRESS_RESET);
*rp++ = vgar (ba, VDAC_DATA) << 2;
*gp++ = vgar (ba, VDAC_DATA) << 2;
*bp++ = vgar (ba, VDAC_DATA) << 2;
vgar(ba, ACT_ADDRESS_RESET);
return vgar (ba, ACT_ADDRESS_R);
return vgar (ba, SEQ_ADDRESS_R);
return vgar (ba, CRT_ADDRESS_R);
return vgar (ba, GCT_ADDRESS_R);
*rp++ = vgar (ba, VDAC_REG_DATA);
*gp++ = vgar (ba, VDAC_REG_DATA);
*bp++ = vgar (ba, VDAC_REG_DATA);
pos->x = vgar (ba, SEQ_ID_CURSOR_X_LOC_LO) |
(vgar (ba, SEQ_ID_CURSOR_X_LOC_HI) << 8);
pos->y = vgar (ba, SEQ_ID_CURSOR_Y_LOC_LO) |
(vgar (ba, SEQ_ID_CURSOR_Y_LOC_HI) << 8);
info->enable = vgar (ba, SEQ_ID_CURSOR_CONTROL) & 0x01;
info->hot.x = vgar (ba, SEQ_ID_CURSOR_X_INDEX) & 0x1f;
info->hot.y = vgar (ba, SEQ_ID_CURSOR_Y_INDEX) & 0x7f;
index = vgar (ba, SEQ_ID_CURSOR_COLOR0);
index = vgar (ba, SEQ_ID_CURSOR_COLOR1);
control = vgar (ba, SEQ_ID_CURSOR_CONTROL);
vgar (ba, GREG_STATUS1_R);
vgar (ba, GREG_STATUS1_R);
vgar (ba, GREG_STATUS1_R);
return vgar (ba, ACT_ADDRESS_R);
return vgar (ba, SEQ_ADDRESS_R);
return vgar (ba, CRT_ADDRESS_R);
return vgar (ba, GCT_ADDRESS_R);
if(vgar(ba, GREG_STATUS1_R)) \
if(vgar(ba, GREG_STATUS1_R))
return vgar(ba, ACT_ADDRESS_R);
return vgar(ba, SEQ_ADDRESS_R);
return vgar(ba, CRT_ADDRESS_R);
return vgar(ba, GCT_ADDRESS_R);
vgar(ba, VDAC_ADDRESS); /* clear old state */
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_ADDRESS); /* clear state */
et_regs->misc_output = vgar(ba, GREG_MISC_OUTPUT_R);
et_regs->seg_sel = vgar(ba, GREG_SEGMENTSELECT);
vgar(ba, VDAC_ADDRESS); /* clear old state */
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_MASK);
vgar(ba, VDAC_ADDRESS); /* clear state */