urtwn_write_4
urtwn_write_4(sc, R92C_HMEBOX(fwcur),
urtwn_write_4(sc, R92C_HMEBOX(fwcur),
urtwn_write_4(sc, R92C_LLT_INIT,
urtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf);
urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32));
urtwn_write_4(sc, R92C_RCR,
urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
urtwn_write_4(sc, R92C_RCR,
urtwn_write_4(sc, R92C_RCR,
urtwn_write_4(sc, R92C_RCR,
urtwn_write_4(sc, R92C_RCR,
urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0]));
urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4]));
urtwn_write_4(sc, R92C_RCR,
urtwn_write_4(sc, R92C_RCR,
urtwn_write_4(sc, R92C_TCR, reg);
urtwn_write_4(sc, R92C_TCR, reg);
urtwn_write_4(sc, ac2reg[ac],
static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t);
urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc,
urtwn_write_4(sc, R92E_AUTO_LLT, val);
#define urtwn_bb_write urtwn_write_4
urtwn_write_4(sc, R92C_MCUFWDL, reg);
urtwn_write_4(sc, R92C_MCUFWDL, reg);
urtwn_write_4(sc, R92C_RQPN,
urtwn_write_4(sc, R92C_RQPN, 0x808e000d);
urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb);
urtwn_write_4(sc, R92C_CAMWRITE, content);
urtwn_write_4(sc, R92C_CAMCMD, command);
urtwn_write_4(sc, R92C_CAMWRITE, content);
urtwn_write_4(sc, R92C_CAMCMD, command);
urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR);
urtwn_write_4(sc, R92C_RCR,
urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff);
urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff);
urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324);
urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226);
urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM);
urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i),
urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]);
urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]);
urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]);
urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]);
urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]);
urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4);
urtwn_write_4(sc, R88E_HISR, 0xffffffff);
urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
urtwn_write_4(sc, R92C_HISR, 0xffffffff);
urtwn_write_4(sc, R92C_HIMR, 0xffffffff);
urtwn_write_4(sc, R92C_CR, reg);
urtwn_write_4(sc, R92C_RRSR, reg);
urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000);
urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404);
urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201);
urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605);
urtwn_write_4(sc, R92C_TDECTRL, reg);
urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
urtwn_write_4(sc, 0x20c, 0xfd0320);
urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg);