urtwn_write_2
urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
urtwn_write_2(sc, R92C_SYS_FUNC_EN,
urtwn_write_2(sc, R92C_SYS_CLKR,
urtwn_write_2(sc, R92C_RRSR, rrsr_mask);
urtwn_write_2(sc, R92C_RXFLTMAP2, 0);
urtwn_write_2(sc, R92C_RXFLTMAP2, 0);
urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval);
urtwn_write_2(sc, R92C_BCNTCFG, 0x000f);
static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t);
urtwn_write_2(sc, R92C_APS_FSMCO,
urtwn_write_2(sc, R92C_APS_FSMCO,
urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
urtwn_write_2(sc, R92C_CR, reg);
urtwn_write_2(sc, R92C_APS_FSMCO,
urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc,
urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc,
urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc,
urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc,
urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc,
urtwn_write_2(sc, R92C_CR, 0x00);
urtwn_write_2(sc, R92C_CR, reg);
urtwn_write_2(sc, R92C_CR, 0);
urtwn_write_2(sc, R92C_CR, reg);
urtwn_write_2(sc, R92C_SYS_FUNC_EN,
urtwn_write_2(sc,R92C_RSV_CTRL, reg);
urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN);
urtwn_write_2(sc,R92C_RSV_CTRL, reg);
urtwn_write_2(sc, R92C_SYS_FUNC_EN,
urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff);
urtwn_write_2(sc, R92C_RQPN_NPQ, 0);
urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d);
urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff);
urtwn_write_2(sc, R92C_SYS_FUNC_EN,
urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff);
urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000);
urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a);
urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a);
urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a);
urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a);
urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc,
urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA);
urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR);
urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1);
urtwn_write_2(sc, R92C_SPEC_SIFS,
urtwn_write_2(sc, R92C_RL,
urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010);
urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
urtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
urtwn_write_2(sc, 0x4ca, 0x0708);
urtwn_write_2(sc, R92C_CR,
urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3);
urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F);
urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000);
urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg);
urtwn_write_2(sc, R92C_LEDCFG0, 0x8080);
urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3);
urtwn_write_2(sc, R92C_APS_FSMCO,