urtwn_read_4
if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
reg = urtwn_read_4(sc, R92C_SYS_CFG);
if (MS(urtwn_read_4(sc, R92C_HPON_FSM),
urtwn_read_4(sc, R92C_RCR) |
urtwn_read_4(sc, R92C_RCR) &
urtwn_read_4(sc, R92C_RCR) &
urtwn_read_4(sc, R92C_RCR) &
urtwn_read_4(sc, R92C_RCR) |
urtwn_read_4(sc, R92C_RCR) |
urtwn_read_4(sc, R92C_RCR) &
reg = urtwn_read_4(sc, R92C_TCR);
static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t);
if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){
urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc,
val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN;
val = urtwn_read_4(sc, R92E_AUTO_LLT);
reg = urtwn_read_4(sc, R92C_MCUFWDL);
#define urtwn_bb_read urtwn_read_4
if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
reg = urtwn_read_4(sc, R92C_MCUFWDL);
if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
odfm0_agccore_regs[i] = urtwn_read_4(sc,
iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG);
ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A);
ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B);
rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0));
rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i));
reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING);
reg = urtwn_read_4(sc, R92C_CR);
reg = urtwn_read_4(sc, R92C_RRSR);
reg = urtwn_read_4(sc, R92C_TDECTRL);
reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;