urtwn_read_2
reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
reg = urtwn_read_2(sc, R92C_SYS_CLKR);
static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t);
urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR);
reg = urtwn_read_2(sc, R92C_CR);
urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc,
urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc,
urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc,
urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc,
urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc,
val = urtwn_read_2(sc, R92C_APS_FSMCO) &
reg = urtwn_read_2(sc, R92C_CR);
reg = urtwn_read_2(sc, R92C_CR);
reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN);
reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN;
reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN;
urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
reg = urtwn_read_2(sc, R92C_USB_EP + 1);
reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc,
urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN |
reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0;