urtwn_bb_write
urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
urtwn_bb_write(sc, 0xe74, reg);
urtwn_bb_write(sc, 0xe78, reg);
urtwn_bb_write(sc, 0xe7c, reg);
urtwn_bb_write(sc, 0xe80, reg);
urtwn_bb_write(sc, 0xe88, reg);
urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]);
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
urtwn_bb_write(sc, R92C_AFE_CTRL3,
urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved);
urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
urtwn_bb_write(sc, 0x818, reg);
urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
urtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
urtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
urtwn_bb_write(sc, addaReg[i],
urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM);
urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT);
urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT);
urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING);
urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING);
urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING);
urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0);
urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2);
urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1);
urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0);
urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE);
urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE);
urtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
urtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
urtwn_bb_write(sc, addaReg[i], addaBackup[i]);
urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0),