urtwn_bb_read
reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) {
val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
reg = urtwn_bb_read(sc, 0xe74);
reg = urtwn_bb_read(sc, 0xe78);
reg = urtwn_bb_read(sc, 0xe7c);
reg = urtwn_bb_read(sc, 0xe80);
reg = urtwn_bb_read(sc, 0xe88);
reg = urtwn_bb_read(sc, R92C_AFE_CTRL3);
reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask;
reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask;
reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);
reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);
urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
reg = urtwn_bb_read(sc, 0x818);
urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
addaBackup[i] = urtwn_bb_read(sc, addaReg[i]);
piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) &
urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))|
urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))|
urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) &
urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) &
reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13));