Symbol: DDR_BASE
sys/arch/arm/broadcom/bcm53xx_board.c
153
const uint32_t v01 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_01);
sys/arch/arm/broadcom/bcm53xx_board.c
154
const uint32_t v82 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_82);
sys/arch/arm/broadcom/bcm53xx_board.c
155
const uint32_t v86 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_86);
sys/arch/arm/broadcom/bcm53xx_board.c
156
const uint32_t v87 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_87);
sys/arch/arm/broadcom/bcm53xx_board.c
405
DDR_BASE + DDR_PHY_CTL_PLL_STATUS);
sys/arch/arm/broadcom/bcm53xx_board.c
407
DDR_BASE + DDR_PHY_CTL_PLL_DIVIDERS);
sys/arch/arm/broadcom/bcm53xx_ccb.c
115
{ "bcmddr", DDR_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT, 1, { IRQ_DDR_CONTROLLER } },