txreg_t
txreg_t reg32;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg, pos;
txreg_t reg = txsibsf0_reg_read(tc, UCB1200_IO_DATA_REG);
txreg_t reg;
txreg_t reg;
txreg_t val;
txreg_t val;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reghi, reglo, oreghi, oreglo;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t he_mask;
txreg_t sc_le_mask[TX39_INTRSET_MAX + 1];
txreg_t sc_regs[TX39_INTRSET_MAX + 1];
txreg_t reg, *regs;
txreg_t reg, pend, *regs;
txreg_t he_mask;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg, pos;
txreg_t reg = tx_conf_read(sc->sc_tc, TX39_IOCTRL_REG);
txreg_t reg, pos, iostat;
txreg_t reg;
txreg_t reg = tx_conf_read(sc->sc_tc, TX392X_IODATAINOUT_REG);
txreg_t reg, pos, iostat;
txreg_t reg;
txreg_t dir, in, out, power;
txreg_t debounce; /* IO */
txreg_t select; /* MFIO */
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg, *iregs = sc->sc_icu_state;
txreg_t reg;
txreg_t sc_icu_state[TX39_INTRSET_MAX + 1];
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg;
(*((volatile txreg_t *)(TX39_SYSADDR_CONFIG_REG_KSEG1 + (reg)))))
(*((volatile txreg_t *)(TX39_SYSADDR_CONFIG_REG_KSEG1 + (reg))) \
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg;
txreg_t reg, reg1;
txreg_t reg;
txreg_t reg;