txq_descs
volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo];
volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi];
if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) {
volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi];
(n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \
if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) {
txq->txq_descs =
for (i = 0, txd = txq->txq_descs,
txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr =
txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]);
txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts,
txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts,
volatile struct gt_eth_desc *txq_descs; /* ptr to tx descriptors */
(uint64_t)txq->txq_descs[j].wtx_addr.wa_high << 32 |
txq->txq_descs[j].wtx_addr.wa_low);
txq->txq_descs[j].wtx_fields.wtxu_vlan,
txq->txq_descs[j].wtx_fields.wtxu_options,
txq->txq_descs[j].wtx_fields.wtxu_status,
txq->txq_descs[j].wtx_cmdlen);
txd = &txq->txq_descs[nexttx];
memset(txq->txq_descs, 0, WM_TXDESCS_SIZE(txq));
&txq->txq_descs[txq->txq_next];
&txq->txq_descs[nexttx].wtx_addr, curaddr);
txq->txq_descs[nexttx].wtx_cmdlen
txq->txq_descs[nexttx].wtx_fields.wtxu_status
txq->txq_descs[nexttx].wtx_fields.wtxu_options
txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0;
txq->txq_descs[lasttx].wtx_cmdlen |=
txq->txq_descs[lasttx].wtx_cmdlen |=
txq->txq_descs[lasttx].wtx_fields.wtxu_vlan
lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen)));
wm_set_dma_addr(&txq->txq_descs[nexttx].wtx_addr,
txq->txq_descs[nexttx].wtx_cmdlen =
txq->txq_descs[nexttx].wtx_fields.wtxu_status = 0;
txq->txq_descs[nexttx].wtx_fields.wtxu_options = 0;
txq->txq_descs[nexttx].wtx_cmdlen |=
txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =
txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0;
txq->txq_descs[lasttx].wtx_cmdlen |=
lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen)));
txq->txq_descs[txs->txs_lastdesc].wtx_fields.wtxu_status;