tx_conf_write
tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32);
tx_conf_write(tc, TX39_INTRCLEAR4_REG,
tx_conf_write(tc, TX39_INTRCLEAR4_REG, TX39_INTRSTATUS4_OPTPOINTINT);
tx_conf_write(tc, TX39_INTRCLEAR4_REG, TX39_INTRSTATUS4_OPTPOINTINT);
tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
tx_conf_write(tc, TX39_SIBCTRL_REG,
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
tx_conf_write(tc, TX39_SIBSNDTXSTART_REG,
tx_conf_write(tc, TX39_SIBSIZE_REG,
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, TX39_SIBSF0_SNDVALID);
tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);
tx_conf_write(tc, TX39_SIBSNDHOLD_REG,
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, TX39_SIBSF0_SNDVALID);
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg);
tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg);
tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg);
tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
tx_conf_write(tc, TX3912_VIDEOCTRL8_REG,
tx_conf_write(tc, TX3912_VIDEOCTRL9_REG,
tx_conf_write(tc, TX3912_VIDEOCTRL10_REG,
tx_conf_write(tc, TX3912_VIDEOCTRL11_REG,
tx_conf_write(tc, TX3912_VIDEOCTRL12_REG,
tx_conf_write(tc, TX3912_VIDEOCTRL13_REG,
tx_conf_write(tc, TX3912_VIDEOCTRL14_REG,
tx_conf_write(tc, TX3912_VIDEOCTRL5_REG,
tx_conf_write(tc, TX3912_VIDEOCTRL6_REG,
tx_conf_write(tc, TX3912_VIDEOCTRL7_REG,
tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
tx_conf_write(tc, TX39_TIMERCONTROL_REG, 0);
tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg);
tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
tx_conf_write(tc, TX39_TIMERALARMHI_REG, t.t_hi);
tx_conf_write(tc, TX39_TIMERALARMLO_REG, t.t_lo);
tx_conf_write(tc, TX39_INTRENABLE1_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE2_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE3_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE4_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE5_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE7_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE8_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
tx_conf_write(tc, TX39_INTRCLEAR1_REG,
tx_conf_write(tc, TX39_INTRCLEAR2_REG,
tx_conf_write(tc, TX39_INTRCLEAR3_REG,
tx_conf_write(tc, TX39_INTRCLEAR4_REG,
tx_conf_write(tc, TX39_INTRCLEAR5_REG,
tx_conf_write(tc, TX39_INTRCLEAR7_REG,
tx_conf_write(tc, TX39_INTRCLEAR8_REG,
tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
tx_conf_write(tc, ofs, reg);
tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
tx_conf_write(tc, TX39_INTRCLEAR5_REG,
tx_conf_write(tc, ofs, he_mask);
tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
tx_conf_write(tc, ofs, reg);
tx_conf_write(tc, ofs, reg);
tx_conf_write(tc, TX39_IOMFIODATAOUT_REG, reg);
tx_conf_write(tc, TX39_IOCTRL_REG, reg);
tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
tx_conf_write(tc, TX39_IRCTRL1_REG, reg);
tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
tx_conf_write(tc, TX39_INTRENABLE6_REG, TX39_INTRENABLE6_GLOBALEN);
tx_conf_write(tc, TX39_INTRENABLE1_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE2_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE3_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE4_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE5_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE7_REG, 0);
tx_conf_write(tc, TX39_INTRENABLE8_REG, 0);
tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_NEGONBUTNINT);
tx_conf_write(tc, TX39_INTRENABLE5_REG, TX39_INTRSTATUS5_NEGONBUTNINT);
tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_NEGONBUTNINT);
tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
tx_conf_write(tc, TX39_INTRENABLE6_REG, iregs[0]);
tx_conf_write(tc, TX39_INTRENABLE1_REG, iregs[1]);
tx_conf_write(tc, TX39_INTRENABLE2_REG, iregs[2]);
tx_conf_write(tc, TX39_INTRENABLE3_REG, iregs[3]);
tx_conf_write(tc, TX39_INTRENABLE4_REG, iregs[4]);
tx_conf_write(tc, TX39_INTRENABLE5_REG, iregs[5]);
tx_conf_write(tc, TX39_INTRENABLE7_REG, iregs[7]);
tx_conf_write(tc, TX39_INTRENABLE8_REG, iregs[8]);
tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);
tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
tx_conf_write(tc, TX39_INTRSTATUS1_REG, TX39_INTRSTATUS1_SIBSF0INT);
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIBUFAVAILINT);
tx_conf_write(tc, TX39_SPITXHOLD_REG , w & 0xffff);
tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIRCVINT);
tx_conf_write(tc, TX39_SPICTRL_REG, reg);
tx_conf_write(tc, TX39_SPICTRL_REG, TX39_SPICTRL_DELAYVAL_SET(reg, n));
tx_conf_write(tc, TX39_SPICTRL_REG, TX39_SPICTRL_BAUDRATE_SET(reg, n));
tx_conf_write(tc, TX39_SPICTRL_REG, reg);
tx_conf_write(tc, TX39_SPICTRL_REG, reg);
tx_conf_write(tc, TX39_SPICTRL_REG, reg);
tx_conf_write(tc, TX39_SPICTRL_REG, reg);
tx_conf_write(tc, TX39_SPICTRL_REG, reg);
tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIBUFAVAILINT);
tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIERRINT);
tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIRCVINT);
tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIEMPTYINT);
tx_conf_write(tc, TX39_UARTTXHOLD_REG(slot),
tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
tx_conf_write(tc, ofs, 0);
tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
tx_conf_write(tc, ofs, reg);
tx_conf_write(tc, ofs, reg);
tx_conf_write(tc, TX39_UARTCTRL1_REG(slot), reg);
tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
tx_conf_write(tc, ofs, reg);
tx_conf_write(tc, TX39_UARTTXHOLD_REG(chip->sc_slot),
tx_conf_write(chip->sc_tc, ofs, reg);
tx_conf_write(chip->sc_tc, ofs, reg);
tx_conf_write(chip->sc_tc, ofs, reg1);
tx_conf_write(chip->sc_tc, TX39_UARTCTRL2_REG(chip->sc_slot), reg);
tx_conf_write(chip->sc_tc, ofs, reg1);
tx_conf_write(chip->sc_tc, TX39_UARTTXHOLD_REG(chip->sc_slot),
tx_conf_write(tc, TX39_UARTCTRL1_REG(slot), reg);
tx_conf_write(tc, TX39_UARTCTRL1_REG(slot), reg);
tx_conf_write(tc, TX39_UARTTXHOLD_REG(chip->sc_slot),
tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg);
tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg);
tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg);
tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg);
tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg);
tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg);