Symbol: DC_WRITE
sys/arch/arm/nvidia/tegra_drm_mode.c
1140
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
1143
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
1293
DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK);
sys/arch/arm/nvidia/tegra_drm_mode.c
1349
DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK);
sys/arch/arm/nvidia/tegra_drm_mode.c
358
DC_WRITE(crtc, DC_CMD_INT_ENABLE_REG, DC_CMD_INT_V_BLANK);
sys/arch/arm/nvidia/tegra_drm_mode.c
384
DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt);
sys/arch/arm/nvidia/tegra_drm_mode.c
386
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
388
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
448
DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_HI_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
455
DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG, cfg);
sys/arch/arm/nvidia/tegra_drm_mode.c
466
DC_WRITE(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG, cfg);
sys/arch/arm/nvidia/tegra_drm_mode.c
469
DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
474
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
476
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
483
DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt);
sys/arch/arm/nvidia/tegra_drm_mode.c
486
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
488
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
517
DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
522
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
524
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
583
DC_WRITE(tegra_crtc, DC_WINC_A_COLOR_DEPTH_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
588
DC_WRITE(tegra_crtc, DC_WINC_A_BYTE_SWAP_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
593
DC_WRITE(tegra_crtc, DC_WINC_A_H_INITIAL_DDA_REG, 0);
sys/arch/arm/nvidia/tegra_drm_mode.c
594
DC_WRITE(tegra_crtc, DC_WINC_A_V_INITIAL_DDA_REG, 0);
sys/arch/arm/nvidia/tegra_drm_mode.c
595
DC_WRITE(tegra_crtc, DC_WINC_A_DDA_INCREMENT_REG, 0x10001000);
sys/arch/arm/nvidia/tegra_drm_mode.c
598
DC_WRITE(tegra_crtc, DC_WINC_A_POSITION_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
601
DC_WRITE(tegra_crtc, DC_WINC_A_SIZE_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
604
DC_WRITE(tegra_crtc, DC_WINC_A_PRESCALED_SIZE_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
608
DC_WRITE(tegra_crtc, DC_WINC_A_LINE_STRIDE_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
615
DC_WRITE(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
619
DC_WRITE(tegra_crtc, DC_DISP_DISP_TIMING_OPTIONS_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
621
DC_WRITE(tegra_crtc, DC_DISP_DISP_COLOR_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
624
DC_WRITE(tegra_crtc, DC_DISP_DISP_SIGNAL_OPTIONS0_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
626
DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
633
DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_POSITION_A_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
640
DC_WRITE(tegra_crtc, DC_DISP_DISP_CLOCK_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
645
DC_WRITE(tegra_crtc, DC_DISP_REF_TO_SYNC_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
648
DC_WRITE(tegra_crtc, DC_DISP_SYNC_WIDTH_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
651
DC_WRITE(tegra_crtc, DC_DISP_BACK_PORCH_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
654
DC_WRITE(tegra_crtc, DC_DISP_FRONT_PORCH_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
657
DC_WRITE(tegra_crtc, DC_DISP_DISP_ACTIVE_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
676
DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_HI_REG, (paddr >> 32) & 3);
sys/arch/arm/nvidia/tegra_drm_mode.c
677
DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_REG, paddr & 0xffffffff);
sys/arch/arm/nvidia/tegra_drm_mode.c
680
DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_H_OFFSET_REG, x);
sys/arch/arm/nvidia/tegra_drm_mode.c
681
DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_V_OFFSET_REG, y);
sys/arch/arm/nvidia/tegra_drm_mode.c
684
DC_WRITE(tegra_crtc, DC_WINBUF_A_SURFACE_KIND_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
700
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
702
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
717
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
719
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
736
DC_WRITE(tegra_crtc, DC_CMD_STATE_ACCESS_REG, 0);
sys/arch/arm/nvidia/tegra_drm_mode.c
739
DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_WINDOW_HEADER_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
749
DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_COMMAND_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
765
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
sys/arch/arm/nvidia/tegra_drm_mode.c
768
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,