sys/arch/arm/imx/imx51_ipuv3.c

302

imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NL, 5, 3);

sys/arch/arm/imx/imx51_ipuv3.c

303

imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOL, 6, 2);

sys/arch/arm/imx/imx51_ipuv3.c

304

imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_DATA, 7, 1);

sys/arch/arm/imx/imx51_ipuv3.c

305

imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NF, 0, 0);

sys/arch/arm/imx/imx51_ipuv3.c

306

imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NFIELD, 0, 0);

sys/arch/arm/imx/imx51_ipuv3.c

307

imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOF, 0, 0);

sys/arch/arm/imx/imx51_ipuv3.c

308

imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOFIELD, 0, 0);

sys/arch/arm/imx/imx51_ipuv3.c

309

imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_CHAN, 0, 0);

sys/arch/arm/imx/imx51_ipuv3.c

310

imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_ADDR, 0, 0);