Symbol: tlb
sys/arch/arc/arc/minidebug.c
950
struct tlb tlb;
sys/arch/arc/arc/minidebug.c
955
mips3_TLBRead(tlbno, &tlb);
sys/arch/arc/arc/minidebug.c
956
if (tlb.tlb_lo0 & MIPS3_PG_V || tlb.tlb_lo1 & MIPS3_PG_V) {
sys/arch/arc/arc/minidebug.c
957
printf("TLB %2d vad 0x%08x ", tlbno, tlb.tlb_hi);
sys/arch/arc/arc/minidebug.c
959
printf("TLB*%2d vad 0x%08x ", tlbno, tlb.tlb_hi);
sys/arch/arc/arc/minidebug.c
961
printf("0=0x%08x ", mips_tlbpfn_to_paddr(tlb.tlb_lo0));
sys/arch/arc/arc/minidebug.c
962
printf("%c", tlb.tlb_lo0 & MIPS3_PG_M ? 'M' : ' ');
sys/arch/arc/arc/minidebug.c
963
printf("%c", tlb.tlb_lo0 & MIPS3_PG_G ? 'G' : ' ');
sys/arch/arc/arc/minidebug.c
964
printf(" atr %x ", (tlb.tlb_lo0 >> 3) & 7);
sys/arch/arc/arc/minidebug.c
965
printf("1=0x%08x ", mips_tlbpfn_to_paddr(tlb.tlb_lo1));
sys/arch/arc/arc/minidebug.c
966
printf("%c", tlb.tlb_lo1 & MIPS3_PG_M ? 'M' : ' ');
sys/arch/arc/arc/minidebug.c
967
printf("%c", tlb.tlb_lo1 & MIPS3_PG_G ? 'G' : ' ');
sys/arch/arc/arc/minidebug.c
968
printf(" atr %x ", (tlb.tlb_lo1 >> 3) & 7);
sys/arch/arc/arc/minidebug.c
969
printf(" sz=%x\n", tlb.tlb_mask);
sys/arch/emips/emips/interrupt.c
80
struct tlbmask tlb;
sys/arch/emips/emips/interrupt.c
85
tlb.tlb_hi = INTERRUPT_CONTROLLER_DEFAULT_ADDRESS;
sys/arch/emips/emips/interrupt.c
86
tlb.tlb_lo0 = INTERRUPT_CONTROLLER_DEFAULT_ADDRESS | 0xf02;
sys/arch/emips/emips/interrupt.c
87
tlb_write_entry(4, &tlb);
sys/arch/emips/emips/interrupt.c
89
tlb.tlb_hi = TIMER_DEFAULT_ADDRESS;
sys/arch/emips/emips/interrupt.c
90
tlb.tlb_lo0 = TIMER_DEFAULT_ADDRESS | 0xf02;
sys/arch/emips/emips/interrupt.c
91
tlb_write_entry(5, &tlb);
sys/arch/emips/emips/xilinx_ml40x.c
121
struct tlbmask tlb;
sys/arch/emips/emips/xilinx_ml40x.c
123
tlb.tlb_hi = USART_DEFAULT_ADDRESS;
sys/arch/emips/emips/xilinx_ml40x.c
124
tlb.tlb_lo0 = USART_DEFAULT_ADDRESS | 0xf02;
sys/arch/emips/emips/xilinx_ml40x.c
125
tlb_write_entry(3, &tlb);
sys/arch/emips/emips/xs_bee3.c
118
struct tlbmask tlb;
sys/arch/emips/emips/xs_bee3.c
120
tlb.tlb_hi = USART_DEFAULT_ADDRESS;
sys/arch/emips/emips/xs_bee3.c
121
tlb.tlb_lo0 = USART_DEFAULT_ADDRESS | 0xf02;
sys/arch/emips/emips/xs_bee3.c
122
tlb_write_entry(3, &tlb);
sys/arch/ews4800mips/stand/common/cop0.c
143
__tlb_pagemask(struct tlb *e)
sys/arch/ews4800mips/stand/common/cop0.c
48
static void __tlb_pagemask(struct tlb *);
sys/arch/ews4800mips/stand/common/cop0.c
72
struct tlb *e;
sys/arch/hppa/include/pte.h
35
#define PTE_PROT(tlb) ((tlb) >> PTE_PROT_SHIFT)
sys/arch/mips/mips/db_interface.c
264
struct tlbmask tlb;
sys/arch/mips/mips/db_interface.c
275
tlb_read_entry(i, &tlb);
sys/arch/mips/mips/db_interface.c
276
if (valid_only && !(tlb.tlb_lo1 & MIPS1_PG_V))
sys/arch/mips/mips/db_interface.c
279
(tlb.tlb_lo1 & MIPS1_PG_V) ? ' ' : '*',
sys/arch/mips/mips/db_interface.c
280
i, tlb.tlb_hi,
sys/arch/mips/mips/db_interface.c
281
tlb.tlb_lo1 & MIPS1_PG_FRAME);
sys/arch/mips/mips/db_interface.c
283
(tlb.tlb_lo1 & MIPS1_PG_D) ? 'D' : ' ',
sys/arch/mips/mips/db_interface.c
284
(tlb.tlb_lo1 & MIPS1_PG_G) ? 'G' : ' ',
sys/arch/mips/mips/db_interface.c
285
(tlb.tlb_lo1 & MIPS1_PG_N) ? 'N' : ' ');
sys/arch/mips/mips/db_interface.c
296
tlb_read_entry(i, &tlb);
sys/arch/mips/mips/db_interface.c
298
!((tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V))
sys/arch/mips/mips/db_interface.c
302
(tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',
sys/arch/mips/mips/db_interface.c
303
tlb_count_width, i, tlb.tlb_hi);
sys/arch/mips/mips/db_interface.c
305
(uint64_t)mips_tlbpfn_to_paddr(tlb.tlb_lo0),
sys/arch/mips/mips/db_interface.c
306
(tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ',
sys/arch/mips/mips/db_interface.c
307
(tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ',
sys/arch/mips/mips/db_interface.c
308
(int)(tlb.tlb_lo0 >> 3) & 7);
sys/arch/mips/mips/db_interface.c
310
(uint64_t)mips_tlbpfn_to_paddr(tlb.tlb_lo1),
sys/arch/mips/mips/db_interface.c
311
(tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ',
sys/arch/mips/mips/db_interface.c
312
(tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ',
sys/arch/mips/mips/db_interface.c
313
(int)(tlb.tlb_lo1 >> 3) & 7,
sys/arch/mips/mips/db_interface.c
314
tlb.tlb_mask);
sys/arch/mips/mips/mips_fixup.c
626
tlb_read_entry(size_t tlbno, struct tlbmask *tlb)
sys/arch/mips/mips/mips_fixup.c
628
(*mips_locore_jumpvec.ljv_tlb_read_entry)(tlbno, tlb);
sys/arch/mips/mips/mips_fixup.c
632
tlb_write_entry(size_t tlbno, const struct tlbmask *tlb)
sys/arch/mips/mips/mips_fixup.c
634
(*mips_locore_jumpvec.ljv_tlb_write_entry)(tlbno, tlb);
sys/arch/mips/mips/wired_map.c
148
tlb.tlb_mask = mips3_wired_map[index].pgmask;
sys/arch/mips/mips/wired_map.c
149
tlb.tlb_hi = mips3_vad_to_vpn(va0);
sys/arch/mips/mips/wired_map.c
151
tlb.tlb_lo0 = MIPS3_PG_G;
sys/arch/mips/mips/wired_map.c
153
tlb.tlb_lo0 =
sys/arch/mips/mips/wired_map.c
158
tlb.tlb_lo1 = MIPS3_PG_G;
sys/arch/mips/mips/wired_map.c
160
tlb.tlb_lo1 = mips3_paddr_to_tlbpfn(
sys/arch/mips/mips/wired_map.c
164
tlb_write_entry(MIPS3_TLB_WIRED_UPAGES + index, &tlb);
sys/arch/mips/mips/wired_map.c
93
struct tlbmask tlb;
sys/arch/powerpc/booke/booke_stubs.c
107
tlb_read_entry(size_t pos, struct tlbmask *tlb)
sys/arch/powerpc/booke/booke_stubs.c
109
(*cpu_md_ops.md_tlb_ops->md_tlb_read_entry)(pos, tlb);
sys/arch/powerpc/booke/booke_stubs.c
115
tlb_write_entry(size_t pos, const struct tlbmask *tlb)
sys/arch/powerpc/booke/booke_stubs.c
117
(*cpu_md_ops.md_tlb_ops->md_tlb_write_entry)(pos, tlb);
sys/arch/powerpc/booke/e500_tlb.c
110
struct e500_tlb tlb;
sys/arch/powerpc/booke/e500_tlb.c
114
tlb.tlb_va = MAS2_EPN & hwtlb.hwtlb_mas2;
sys/arch/powerpc/booke/e500_tlb.c
115
tlb.tlb_size = 1024 << (2 * MASX_TSIZE_GET(hwtlb.hwtlb_mas1));
sys/arch/powerpc/booke/e500_tlb.c
116
tlb.tlb_asid = MASX_TID_GET(hwtlb.hwtlb_mas1);
sys/arch/powerpc/booke/e500_tlb.c
117
tlb.tlb_pte = (hwtlb.hwtlb_mas2 & MAS2_WIMGE)
sys/arch/powerpc/booke/e500_tlb.c
126
tlb.tlb_pte |= (prot_mask & hwtlb.hwtlb_mas3) << prot_shift;
sys/arch/powerpc/booke/e500_tlb.c
127
return tlb;
sys/arch/powerpc/booke/e500_tlb.c
229
tlb_to_hwtlb(const struct e500_tlb tlb)
sys/arch/powerpc/booke/e500_tlb.c
233
KASSERT(trunc_page(tlb.tlb_va) == tlb.tlb_va);
sys/arch/powerpc/booke/e500_tlb.c
234
KASSERT(tlb.tlb_size != 0);
sys/arch/powerpc/booke/e500_tlb.c
235
KASSERT((tlb.tlb_size & (tlb.tlb_size - 1)) == 0);
sys/arch/powerpc/booke/e500_tlb.c
236
const uint32_t prot_mask = tlb.tlb_pte & PTE_RWX_MASK;
sys/arch/powerpc/booke/e500_tlb.c
237
if (__predict_true(tlb.tlb_size == PAGE_SIZE)) {
sys/arch/powerpc/booke/e500_tlb.c
244
if (tlb.tlb_asid) {
sys/arch/powerpc/booke/e500_tlb.c
246
| MASX_TID_MAKE(tlb.tlb_asid);
sys/arch/powerpc/booke/e500_tlb.c
256
if (tlb.tlb_pte & PTE_UNMODIFIED)
sys/arch/powerpc/booke/e500_tlb.c
258
if (tlb.tlb_pte & PTE_UNSYNCED)
sys/arch/powerpc/booke/e500_tlb.c
261
KASSERT(tlb.tlb_asid == 0);
sys/arch/powerpc/booke/e500_tlb.c
262
KASSERT((tlb.tlb_size & 0xaaaaa7ff) == 0);
sys/arch/powerpc/booke/e500_tlb.c
263
u_int cntlz = __builtin_clz(tlb.tlb_size);
sys/arch/powerpc/booke/e500_tlb.c
278
hwtlb.hwtlb_mas2 = tlb.tlb_va | (tlb.tlb_pte & PTE_WIMGE_MASK);
sys/arch/powerpc/booke/e500_tlb.c
279
hwtlb.hwtlb_mas3 |= tlb.tlb_pte & PTE_RPN_MASK;
sys/arch/powerpc/booke/e500_tlb.c
581
e500_tlb_write_entry(size_t index, const struct tlbmask *tlb)
sys/arch/powerpc/booke/e500_tlb.c
586
e500_tlb_read_entry(size_t index, struct tlbmask *tlb)
sys/arch/powerpc/booke/e500_tlb.c
619
struct e500_tlb tlb = hwtlb_to_tlb(hwtlb);
sys/arch/powerpc/booke/e500_tlb.c
626
tlb.tlb_va, tlb.tlb_asid, tlb.tlb_pte);
sys/arch/powerpc/booke/e500_tlb.c
628
tlb.tlb_pte & PTE_RPN_MASK,
sys/arch/powerpc/booke/e500_tlb.c
629
tlb.tlb_pte & PTE_xR ? "R" : "",
sys/arch/powerpc/booke/e500_tlb.c
630
tlb.tlb_pte & PTE_xW ? "W" : "",
sys/arch/powerpc/booke/e500_tlb.c
631
tlb.tlb_pte & PTE_UNMODIFIED ? "*" : "",
sys/arch/powerpc/booke/e500_tlb.c
632
tlb.tlb_pte & PTE_xX ? "X" : "",
sys/arch/powerpc/booke/e500_tlb.c
633
tlb.tlb_pte & PTE_UNSYNCED ? "*" : "",
sys/arch/powerpc/booke/e500_tlb.c
634
tlb.tlb_pte & PTE_W ? "W" : "",
sys/arch/powerpc/booke/e500_tlb.c
635
tlb.tlb_pte & PTE_I ? "I" : "",
sys/arch/powerpc/booke/e500_tlb.c
636
tlb.tlb_pte & PTE_M ? "M" : "",
sys/arch/powerpc/booke/e500_tlb.c
637
tlb.tlb_pte & PTE_G ? "G" : "",
sys/arch/powerpc/booke/e500_tlb.c
638
tlb.tlb_pte & PTE_E ? "E" : "");
sys/arch/powerpc/booke/e500_tlb.c
668
struct e500_tlb tlb = hwtlb_to_tlb(hwtlb);
sys/arch/powerpc/booke/e500_tlb.c
669
if (!(*func)(ctx, tlb.tlb_va, tlb.tlb_asid,
sys/arch/powerpc/booke/e500_tlb.c
670
tlb.tlb_pte))
sys/arch/sparc/stand/ofwboot/loadfile_machdep.c
761
bi_itlb->tlb[i].te_va = itlb_store[i].te_va;
sys/arch/sparc/stand/ofwboot/loadfile_machdep.c
762
bi_itlb->tlb[i].te_pa = itlb_store[i].te_pa;
sys/arch/sparc/stand/ofwboot/loadfile_machdep.c
767
bi_dtlb->tlb[i].te_va = dtlb_store[i].te_va;
sys/arch/sparc/stand/ofwboot/loadfile_machdep.c
768
bi_dtlb->tlb[i].te_pa = dtlb_store[i].te_pa;
sys/arch/sparc64/include/bootinfo.h
121
struct tlb_entry tlb[1];
sys/arch/sparc64/sparc64/autoconf.c
375
kernel_tlbs = &bi_tlb->tlb[0];
sys/arch/usermode/usermode/pmap.c
338
tlb = (struct pv_entry **) kmem_kvm_cur_start;
sys/arch/usermode/usermode/pmap.c
340
addr = thunk_mmap(tlb, pm_entries_size,
sys/arch/usermode/usermode/pmap.c
344
if (addr != (void *) tlb)
sys/arch/usermode/usermode/pmap.c
347
memset(tlb, 0, pm_entries_size); /* test and clear */
sys/arch/usermode/usermode/pmap.c
413
va = (vaddr_t) tlb + pg;
sys/arch/usermode/usermode/pmap.c
712
if (tlb[pv->pv_lpn] == NULL) {
sys/arch/usermode/usermode/pmap.c
800
tlb[pv->pv_lpn] = NULL;
sys/arch/usermode/usermode/pmap.c
802
tlb[pv->pv_lpn] = pv;
sys/arch/usermode/usermode/pmap.c
814
if (!tlb[pv->pv_lpn])
sys/arch/usermode/usermode/pmap.c
817
if (tlb[pv->pv_lpn]->pv_mmap_ppl == THUNK_PROT_NONE)
sys/arch/usermode/usermode/pmap.c
829
tlb[pv->pv_lpn] = NULL;
sys/arch/usermode/usermode/pmap.c
90
static struct pv_entry **tlb; /* current tlb mappings (direct mapped) */