tegra_crtc
#define to_tegra_crtc(x) container_of(x, struct tegra_crtc, base)
DC_SET_CLEAR(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG,
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
struct tegra_crtc *tegra_crtc = priv;
struct drm_device *ddev = tegra_crtc->base.dev;
const uint32_t status = DC_READ(tegra_crtc, DC_CMD_INT_STATUS_REG);
DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK);
atomic_inc_32(&sc->sc_vbl_received[tegra_crtc->index]);
drm_handle_vblank(ddev, tegra_crtc->index);
struct tegra_crtc *tegra_crtc = NULL;
tegra_crtc = to_tegra_crtc(iter);
if (tegra_crtc == NULL)
DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, DC_CMD_INT_V_BLANK, 0);
struct tegra_crtc *tegra_crtc = NULL;
tegra_crtc = to_tegra_crtc(iter);
if (tegra_crtc == NULL)
DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, 0, DC_CMD_INT_V_BLANK);
DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK);
struct tegra_crtc *crtc;
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
if (tegra_crtc->enabled == false)
opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG);
DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt);
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
handle, tegra_crtc->index);
struct drm_gem_cma_object *cursor_obj = tegra_crtc->cursor_obj;
DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_HI_REG,
DC_READ(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG);
DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG, cfg);
cfg = DC_READ(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG);
DC_WRITE(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG, cfg);
DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG,
__SHIFTIN(tegra_crtc->cursor_x, DC_DISP_CURSOR_POSITION_H) |
__SHIFTIN(tegra_crtc->cursor_y, DC_DISP_CURSOR_POSITION_V));
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG);
DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt);
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
while (DC_READ(tegra_crtc, DC_CMD_STATE_CONTROL_REG) &
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
tegra_crtc->cursor_x = x & 0x3fff;
tegra_crtc->cursor_y = y & 0x3fff;
DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG,
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
if (tegra_crtc->ih) {
intr_disestablish(tegra_crtc->ih);
drm_gem_cma_free_object(&tegra_crtc->cursor_obj->base);
bus_space_unmap(tegra_crtc->bst, tegra_crtc->bsh, tegra_crtc->size);
kmem_free(tegra_crtc, sizeof(*tegra_crtc));
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG,
DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG,
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
DC_WRITE(tegra_crtc, DC_WINC_A_COLOR_DEPTH_REG,
DC_WRITE(tegra_crtc, DC_WINC_A_BYTE_SWAP_REG,
DC_WRITE(tegra_crtc, DC_WINC_A_H_INITIAL_DDA_REG, 0);
DC_WRITE(tegra_crtc, DC_WINC_A_V_INITIAL_DDA_REG, 0);
DC_WRITE(tegra_crtc, DC_WINC_A_DDA_INCREMENT_REG, 0x10001000);
DC_WRITE(tegra_crtc, DC_WINC_A_POSITION_REG,
DC_WRITE(tegra_crtc, DC_WINC_A_SIZE_REG,
DC_WRITE(tegra_crtc, DC_WINC_A_PRESCALED_SIZE_REG,
DC_WRITE(tegra_crtc, DC_WINC_A_LINE_STRIDE_REG,
DC_WRITE(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG,
DC_WRITE(tegra_crtc, DC_DISP_DISP_TIMING_OPTIONS_REG,
DC_WRITE(tegra_crtc, DC_DISP_DISP_COLOR_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_DISP_DISP_SIGNAL_OPTIONS0_REG,
DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_POSITION_A_REG,
const u_int parent_rate = clk_get_rate(tegra_crtc->clk_parent);
DC_WRITE(tegra_crtc, DC_DISP_DISP_CLOCK_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_DISP_REF_TO_SYNC_REG,
DC_WRITE(tegra_crtc, DC_DISP_SYNC_WIDTH_REG,
DC_WRITE(tegra_crtc, DC_DISP_BACK_PORCH_REG,
DC_WRITE(tegra_crtc, DC_DISP_FRONT_PORCH_REG,
DC_WRITE(tegra_crtc, DC_DISP_DISP_ACTIVE_REG,
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_HI_REG, (paddr >> 32) & 3);
DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_REG, paddr & 0xffffffff);
DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_H_OFFSET_REG, x);
DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_V_OFFSET_REG, y);
DC_WRITE(tegra_crtc, DC_WINBUF_A_SURFACE_KIND_REG,
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
DC_WRITE(tegra_crtc, DC_CMD_STATE_ACCESS_REG, 0);
DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_WINDOW_HEADER_REG,
struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_COMMAND_REG,
DC_SET_CLEAR(tegra_crtc, DC_CMD_DISPLAY_POWER_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
tegra_crtc->enabled = true;
struct tegra_crtc *tegra_crtc = to_tegra_crtc(encoder->crtc);
input_ctrl = __SHIFTIN(tegra_crtc->index,