sm_ddr4
s->sm_ddr4.ddr4_mod_type <
type = spdmem_ddr4_module_types[s->sm_ddr4.ddr4_mod_type];
if ((s->sm_ddr4.ddr4_hybrid)
&& (s->sm_ddr4.ddr4_hybrid_media == 1))
print_part(s->sm_ddr4.ddr4_part_number,
sizeof(s->sm_ddr4.ddr4_part_number));
if (s->sm_ddr4.ddr4_mod_type < __arraycount(spdmem_ddr4_module_types))
spdmem_ddr4_module_types[s->sm_ddr4.ddr4_mod_type]);
(s->sm_ddr4.ddr4_bus_width_extension) ? "" : "no ",
(s->sm_ddr4.ddr4_has_therm_sensor) ? "" : "no ");
dimm_size = (s->sm_ddr4.ddr4_capacity + 28) /* chip_capacity */
+ (s->sm_ddr4.ddr4_primary_bus_width + 3); /* bus width */
switch (s->sm_ddr4.ddr4_device_width) { /* DRAM width */
(s->sm_ddr4.ddr4_package_ranks + 1); /* log.ranks/DIMM */
if (s->sm_ddr4.ddr4_signal_loading == 2) {
dimm_size *= (s->sm_ddr4.ddr4_diecount + 1);
#define __DDR4_VALUE(field) ((s->sm_ddr4.ddr4_##field##_mtb * 125 + \
s->sm_ddr4.ddr4_##field##_ftb) - \
((s->sm_ddr4.ddr4_##field##_ftb > 127)?256:0))
1 << (s->sm_ddr4.ddr4_primary_bus_width + 3),
ranks = s->sm_ddr4.ddr4_package_ranks + 1;
s->sm_ddr4.ddr4_rows + 12, s->sm_ddr4.ddr4_cols + 9,
ranks, (ranks > 1) ? ((s->sm_ddr4.ddr4_rank_mix == 1)
1 << (2 + s->sm_ddr4.ddr4_logbanks),
1 << s->sm_ddr4.ddr4_bankgroups);
tRAS_clocks = (s->sm_ddr4.ddr4_tRASmin_msb * 256 +
s->sm_ddr4.ddr4_tRASmin_lsb) * 125 * 1000 / cycle_time;