single_inst_bset_b
single_inst_bset_b(*draco_intena, DRIRQ_INT6);
single_inst_bset_b(*draco_intena, DRIRQ_INT2);
single_inst_bset_b(draco_ioct->io_status2, DRSTAT2_TMRINTENA);
single_inst_bset_b(*draco_intena, DRIRQ_INT2);
single_inst_bset_b(*draco_intena, DRIRQ_SCSI);
#define DATHI single_inst_bset_b(draco_ioct->io_control, DRCNTRL_KBDDATOUT)
#define CLKHI single_inst_bset_b(draco_ioct->io_control, DRCNTRL_KBDCLKOUT)
single_inst_bset_b(*draco_intena, DRIRQ_INT2);
single_inst_bset_b(MFP2->mf_imrb, IB_SCDM);
single_inst_bset_b(MFP2->mf_imra, IA_SCSI);
single_inst_bset_b(MFP2->mf_imra,
single_inst_bset_b(MFP2->mf_imra, IA_SCSI);
single_inst_bset_b(MFP2->mf_imra, IA_SCSI);
single_inst_bset_b(MFP->mf_imrb, IB_DINT);
single_inst_bset_b(MFP->mf_gpip, 0x08); \
single_inst_bset_b(MFP->mf_gpip, 0x01); \
single_inst_bset_b(MFP->mf_tcdcr, (ospeed >> 8) & 0x0f);
single_inst_bset_b(MFP->mf_imra, (IA_RRDY|IA_RERR|IA_TRDY|IA_TERR));
single_inst_bset_b(MFP->mf_imra, imra);
single_inst_bset_b(MFP->mf_imra, sc->sc_imra);
single_inst_bset_b(MFP->mf_imrb, sc->sc_imrb);
single_inst_bset_b(MFP->mf_tcdcr, (sc->sc_ospeed >> 8) & 0x0f);
single_inst_bset_b(MFP->mf_imra, sc->sc_imra);
single_inst_bset_b(MFP->mf_imrb, sc->sc_imrb);
single_inst_bset_b(MFP->mf_imra, IA_TRDY|IA_TERR);
#define siron(x) single_inst_bset_b((ssir), (x))
single_inst_bset_b(MFP->mf_imrb, IB_ISA1);
single_inst_bset_b(MFP->mf_imra, IA_ISA2);
single_inst_bset_b(MFP->mf_imrb, IB_ISA1);
single_inst_bset_b(MFP->mf_ierb, IB_ISA1);
single_inst_bset_b(MFP->mf_imra, IA_ISA2);
single_inst_bset_b(MFP->mf_iera, IA_ISA2);
single_inst_bset_b(*interrupt_reg, interreg);
single_inst_bset_b(*interrupt_reg, IREG_ALL_ENAB);
single_inst_bset_b(*interrupt_reg, IREG_CLOCK_ENAB_5);
single_inst_bset_b(*interrupt_reg, bit);
single_inst_bset_b(*interrupt_reg, interreg);
single_inst_bset_b(*interrupt_reg, IREG_ALL_ENAB);
single_inst_bset_b(*interrupt_reg, IREG_CLOCK_ENAB_5);