rtwn_write_4
rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d));
rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f));
rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5));
static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t);
rtwn_write_4(sc, R92C_CR, reg);
rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf);
rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32));
rtwn_write_4(sc, R92C_RCR,
rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
rtwn_write_4(sc, R92C_RCR,
rtwn_write_4(sc, R92C_RCR,
rtwn_write_4(sc, R92C_RCR,
rtwn_write_4(sc, R92C_RCR,
rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0]));
rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4]));
rtwn_write_4(sc, R92C_RCR,
rtwn_write_4(sc, R92C_RCR,
rtwn_write_4(sc, R92C_TCR, reg);
rtwn_write_4(sc, R92C_TCR, reg);
rtwn_write_4(sc, aci2reg[aci],
#define rtwn_bb_write rtwn_write_4
rtwn_write_4(sc, R92C_APS_FSMCO, reg);
rtwn_write_4(sc, R92C_AFE_XTAL_CTRL,
rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg);
rtwn_write_4(sc, R92C_INT_MIG, 0);
rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg);
rtwn_write_4(sc, R92C_MCUFWDL, reg);
rtwn_write_4(sc, R92C_MCUFWDL, reg);
rtwn_write_4(sc, R92C_RQPN,
rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13));
rtwn_write_4(sc, R92C_BKQ_DESA,
rtwn_write_4(sc, R92C_BEQ_DESA,
rtwn_write_4(sc, R92C_VIQ_DESA,
rtwn_write_4(sc, R92C_VOQ_DESA,
rtwn_write_4(sc, R92C_BCNQ_DESA,
rtwn_write_4(sc, R92C_MGQ_DESA,
rtwn_write_4(sc, R92C_HQ_DESA,
rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr);
rtwn_write_4(sc, R92C_LEDCFG0,
rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR);
rtwn_write_4(sc, R92C_RCR,
rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff);
rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff);
rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322);
rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222);
rtwn_write_4(sc, R92C_HISR, 0xffffffff);
rtwn_write_4(sc, R92C_HIMR, 0x00000000);
rtwn_write_4(sc, R92C_RRSR, reg);
rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000);
rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504);
rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000);
rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504);
rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
rtwn_write_4(sc, R92C_PIFS, 0x1c);
rtwn_write_4(sc, R92C_MCUTST_1, 0x0);
rtwn_write_4(sc, R92C_HISR, 0xffffffff);
rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE);
rtwn_write_4(sc, R92C_HIMR, 0x00000000);
rtwn_write_4(sc, R92C_HIMR, 0x00000000);
rtwn_write_4(sc, R92C_HISR, status);
rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE);
rtwn_write_4(sc, R92C_HMEBOX(fwcur),
rtwn_write_4(sc, R92C_HMEBOX(fwcur),
rtwn_write_4(sc, R92C_LLT_INIT,
rtwn_write_4(sc, R92C_EFUSE_CTRL, reg);