rtwn_write_1
rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate);
rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate);
static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t);
rtwn_write_1(sc, R92C_BCN_CTRL,
rtwn_write_1(sc, R92C_BCN_CTRL,
rtwn_write_1(sc, R92C_BCN_CTRL,
rtwn_write_1(sc, R92C_LEDCFG2, reg);
rtwn_write_1(sc, R92C_TXPAUSE, 0x0);
rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03);
rtwn_write_1(sc, R92C_BCN_CTRL,
rtwn_write_1(sc, R92C_BCN_CTRL,
rtwn_write_1(sc, R92C_TXPAUSE,
rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0);
rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3);
rtwn_write_1(sc, R92C_TXPAUSE, 0);
rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10);
rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10);
rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10);
rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10);
rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10);
rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10);
rtwn_write_1(sc, R92C_RSV_CTRL, 0);
rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77);
rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22);
rtwn_write_1(sc, R92C_GPIO_MUXCFG,
rtwn_write_1(sc, R92C_APSD_CTRL,
rtwn_write_1(sc, 0xfe10, 0x19);
rtwn_write_1(sc, R92C_HMETFR + 3, 0x20);
rtwn_write_1(sc, off++, buf[i]);
rtwn_write_1(sc, R92C_MCUFWDL,
rtwn_write_1(sc, R92C_MCUFWDL + 2,
rtwn_write_1(sc, R92C_MCUFWDL,
rtwn_write_1(sc, R92C_MCUFWDL,
rtwn_write_1(sc, R92C_MCUFWDL + 1, 0);
rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY);
rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY);
rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY);
rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY);
rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY);
rtwn_write_1(sc, R92C_PBP,
rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val);
rtwn_write_1(sc, R92C_RF_CTRL,
rtwn_write_1(sc, R92C_SYS_FUNC_EN,
rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
rtwn_write_1(sc, 0x16, reg);
rtwn_write_1(sc, R92C_BWOPMODE,
rtwn_write_1(sc, R92C_RRSR + 2, reg);
rtwn_write_1(sc, R92C_BWOPMODE,
rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
rtwn_write_1(sc, R92C_TXPAUSE, 0xff);
rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
rtwn_write_1(sc, R92C_TXPAUSE, 0x00);
rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4);
rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]);
rtwn_write_1(sc, R92C_ACKTO, 0x40);
rtwn_write_1(sc, R92C_DRVERLYINT, 0x05);
rtwn_write_1(sc, R92C_BCNDMATIM, 0x02);
rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0);
rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff);
rtwn_write_1(sc, R92C_GPIO_MUXCFG,
rtwn_write_1(sc, 0x15, 0xe9);
rtwn_write_1(sc, R92C_TXPAUSE, 0xff);
rtwn_write_1(sc, R92C_RF_CTRL, 0x00);
rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg);
rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg);
rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54);
rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */
rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */
rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e);
rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN);