rtwn_read_4
reg = rtwn_read_4(sc, R92C_CR);
static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t);
rtwn_read_4(sc, R92C_RCR) |
rtwn_read_4(sc, R92C_RCR) &
rtwn_read_4(sc, R92C_RCR) &
rtwn_read_4(sc, R92C_RCR) &
rtwn_read_4(sc, R92C_RCR) |
rtwn_read_4(sc, R92C_RCR) |
rtwn_read_4(sc, R92C_RCR) &
reg = rtwn_read_4(sc, R92C_TCR);
#define rtwn_bb_read rtwn_read_4
reg = rtwn_read_4(sc, R92C_APS_FSMCO);
(rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f);
reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL);
reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2);
reg = rtwn_read_4(sc, R92C_MCUFWDL);
if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
reg = rtwn_read_4(sc, R92C_MCUFWDL);
if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000);
reg = rtwn_read_4(sc, R92C_RRSR);
status = rtwn_read_4(sc, R92C_HISR);
status = rtwn_read_4(sc, R92C_HISR);
if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
reg = rtwn_read_4(sc, R92C_SYS_CFG);
if (MS(rtwn_read_4(sc, R92C_HPON_FSM),