rtwn_read_1
static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t);
rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0);
rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN);
rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
rtwn_read_1(sc, R92C_BCN_CTRL) |
rtwn_read_1(sc, R92C_BCN_CTRL) |
rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL);
reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL);
reg = rtwn_read_1(sc, R92C_APSD_CTRL);
rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT);
rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
reg = rtwn_read_1(sc, 0x16);
rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
reg = rtwn_read_1(sc, R92C_RRSR + 2);
rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN);
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))