regwb_pll
regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl);
regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div);
regwb_pll(sc, VCLK_POST_DIV, reg);
regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div);
regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl);